Difference between revisions of "Lecture Notes"
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*[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] | *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] | ||
*[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] | *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] | ||
| + | *[[media:Example3.vhd|VHDL Example 3]] | ||
| + | *[[media:Example4.vhd|VHDL Example 4]] | ||
| + | *[[media:Example5.vhd|VHDL Example 5]] | ||
| + | *[[media:Example6.vhd|VHDL Example 6]] | ||
| + | *[[media:Example7.vhd|VHDL Example 7]] | ||
*[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
*[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
Revision as of 19:16, 30 January 2012
- Standard Cell Example
- Espresso Example
- Espresso Example Output
- Espresso Cyclic Example
- Espresso Cyclic Example Output
- VHDL Example 1
- VHDL Example 1 Synthesized RTL Schematic
- VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 2
- VHDL Example 2 Synthesized RTL Schematic
- VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 3
- VHDL Example 4
- VHDL Example 5
- VHDL Example 6
- VHDL Example 7
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
