Difference between revisions of "Lecture Notes"
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*[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] | *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] | ||
*[[media:Example1.vhd|VHDL Example 1]] | *[[media:Example1.vhd|VHDL Example 1]] | ||
| − | *[[media:Example1RTL.pdf|Synthesized RTL Schematic]] | + | *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] |
| − | *[[media:Example1Technology.pdf|Xilinx Spartan 6 Technology Map Schematic]] | + | *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] |
*[[media:Example2.vhd|VHDL Example 2]] | *[[media:Example2.vhd|VHDL Example 2]] | ||
| − | *[[media:Example2RTL.pdf|Synthesized RTL Schematic]] | + | *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] |
| − | *[[media:Example2Technology.pdf|Xilinx Spartan 6 Technology Map Schematic]] | + | *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] |
*[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
*[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] | ||
Revision as of 15:27, 26 January 2012
- Standard Cell Example
- Espresso Example
- Espresso Example Output
- Espresso Cyclic Example
- Espresso Cyclic Example Output
- VHDL Example 1
- VHDL Example 1 Synthesized RTL Schematic
- VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic
- VHDL Example 2
- VHDL Example 2 Synthesized RTL Schematic
- VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
