Syllabus

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  1. The General Purpose Machine
    1. User's View
    2. Programmer's View
    3. Architect's View
    4. Logic Designer's View
  2. Machines, Machine Languages and Digital Logic
    1. Classification of Computers
      1. 4-, 3-, 2-, 1-, and 0-Address Instructions
      2. Stack-based Machines
      3. General Register Machines (1 1/2 Address Machines)
      4. Load/Store Machines
    2. Instruction Sets
    3. Introduction of the SRC (Simple RISC Computer)
    4. Using RTN (Register Transfer Notation)
    5. Addressing Modes (w/RTN Descriptions)
      1. Immediate Addressing
      2. Direct Addressing
      3. Indirect Addressing
      4. Register Direct Addressing
      5. Register Indirect Addressing
      6. Displacement-based Addressing
      7. Indexed Addressing
      8. Relative Addressing
    6. Hardware Implications of RTN
  3. Processor Design
    1. Introduction to the Design Process
    2. 1-Bus SRC Microarchitecture (w/VHDL Model)*
      1. Data Path
      2. Control
    3. 2-Bus SRC Microarchitecture
    4. 3-Bus SRC Microarchitecture
    5. Reset Considerations
    6. Exceptions/Interrupts
  4. Memory System Design
    1. Components of the Memory System
    2. Memory Types
      1. EPROM
        1. Example: SRC EPROM Memory Subsystem*
      2. SRAM
        1. Example: SRC SRAM Memory Subsystem*
      3. DRAM (FPM, EDO, VRAM)
        1. Example: SRC DRAM Memory Subsystem*
      4. SDRAM (SDRAM, DDR, DDR2)
      5. FLASH Memory
    3. Memory Modules
      1. Example: 72-pin 16 MB FPM DRAM DIMM
      2. Example: 144-pin 64 MB EDO DRAM DIMM
      3. Example: 184-pin 128 MB ECC DDR DRAM DIMM
    4. Two-Level Hierarchy
    5. Cache
      1. Associative Caches*
      2. Direct-Mapped Caches*
      3. N-Way Set-Associative Caches*
      4. Read/Write/Replacement Policies*
    6. Virtual Memory
      1. Segmentation
      2. Paging
      3. Regaining Lost Ground: The TLB
    7. Overall Memory Subsystem with Introduction to I/O Issues
  5. Input/Output
    1. I/O Subsystems Overview
    2. Programmed I/O
      1. General Principles
      2. Example: Programmed I/O on the SRC (w/VHDL Model)*
    3. Interrupt-Driven I/O
    4. DMA (Direct Memory Access)
      1. General Principles
      2. Example: DMA Engine for the SRC (w/VHDL Model)*
      3. Example: PCI(e)
        1. Parallel vs. Serial I/O Buses
    5. I/O Error Detection and Correction*
      1. Parity
      2. Hamming/SECDED Codes (ECC Memory)
      3. CRC Codes
  6. Advanced Topics
    1. Pipelining
      1. General Principles
      2. Example: Pipelined SRC (w/VHDL Model)*
    2. Instruction Level Parallelism
      1. Superscalar Processors
        1. General Principles
        2. Example: Intel Pentium (1st Superscalar X86 CPU)
        3. Example: AMD K7 (9-issue, Speculative Out-of-Order Execution, etc.)
      2. VLIW Machines
        1. General Principles
        2. Example: IBM VLIW Prototype
        3. Example: Intel Itanium/EPIC
    3. Microprogramming
      1. General Principles
      2. Example: Microprogrammed SRC (w/VHDL Model)*
    4. Code Morphing
      1. Example: Transmeta Crusoe
    5. Extending the Address Space
      1. 16- to 32-bit: Intel 80386
      2. 32- to 64-bit: AMD Hammer vs Intel Itanium
    6. Multicore CPUs
      1. Example: Intel i7-980X