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| − | # The General Purpose Machine
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| − | ## User's View
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| − | ## Programmer's View
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| − | ## Architect's View
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| − | ## Logic Designer's View
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| − | # Machines, Machine Languages and Digital Logic
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| − | ## Classification of Computers
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| − | ### 4-, 3-, 2-, 1-, and 0-Address Instructions
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| − | ### Stack-based Machines
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| − | ### General Register Machines (1 1/2 Address Machines)
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| − | ### Load/Store Machines
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| − | ## Instruction Types
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| − | ### Data Movement Instructions
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| − | ### Arithmetic and Logic Instructions
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| − | ### Branch Instructions
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| − | ## Introduction of the SRC (Simple RISC Computer)
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| − | ### SRC Instruction Set
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| − | ### SRC Assembler/Simulator*
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| − | ## Using RTN (Register Transfer Notation)
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| − | ### RTN Description of the SRC*
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| − | ## Addressing Modes (w/RTN Descriptions)
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| − | ### Immediate Addressing
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| − | ### Direct Addressing
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| − | ### Indirect Addressing
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| − | ### Register Direct Addressing
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| − | ### Register Indirect Addressing
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| − | ### Displacement-based Addressing
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| − | ### Indexed Addressing
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| − | ### Relative Addressing
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| − | ## Hardware Implications of RTN
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| − | # Processor Design
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| − | ## Introduction to the Design Process
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| − | ## 1-Bus SRC Microarchitecture (w/VHDL Model)*
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| − | ### Data Path
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| − | ### Control
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| − | ## 2-Bus SRC Microarchitecture
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| − | ## 3-Bus SRC Microarchitecture
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| − | ## Reset Considerations
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| − | ## Exceptions/Interrupts
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| − | # Memory System Design
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| − | ## Components of the Memory System
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| − | ## Memory Types
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| − | ### EPROM
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| − | #### Example: SRC EPROM Memory Subsystem*
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| − | ### SRAM
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| − | #### Example: SRC SRAM Memory Subsystem*
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| − | ### DRAM (FPM, EDO, VRAM)
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| − | #### Example: SRC DRAM Memory Subsystem*
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| − | ### SDRAM (SDRAM, DDR, DDR2)
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| − | ### FLASH Memory
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| − | ## Memory Modules
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| − | ### Example: 72-pin 16 MB FPM DRAM DIMM
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| − | ### Example: 144-pin 64 MB EDO DRAM DIMM
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| − | ### Example: 184-pin 128 MB ECC DDR DRAM DIMM
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| − | ## Two-Level Hierarchy
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| − | ## Cache
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| − | ### Associative Caches*
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| − | ### Direct-Mapped Caches*
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| − | ### N-Way Set-Associative Caches*
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| − | ### Read/Write/Replacement Policies*
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| − | ## Virtual Memory
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| − | ### Segmentation
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| − | ### Paging
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| − | ### Regaining Lost Ground: The TLB
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| − | ## Overall Memory Subsystem with Introduction to I/O Issues
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| − | # Input/Output
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| − | ## I/O Subsystems Overview
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| − | ## Programmed I/O
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| − | ### General Principles
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| − | ### Example: SRC Stereo Audio Card Using Programmed I/O(w/VHDL Model)*
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| − | ## Interrupt-Driven I/O
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| − | ## DMA (Direct Memory Access)
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| − | ### General Principles
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| − | ### Example: SRC Stereo Audio Card Using DMA Engine(w/VHDL Model)*
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| − | ### Example: PCI(e)
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| − | #### Parallel vs. Serial I/O Buses
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| − | ## I/O Error Detection and Correction*
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| − | ### Parity
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| − | ### Hamming/SECDED Codes (ECC Memory)
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| − | ### CRC Codes
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| − | # Peripherals and Peripheral Buses
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| − | ## RS-232C
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| − | ## Universal Serial Bus V2.0
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| − | ## IEEE 1394 (Firewire)
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| − | ## Video
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| − | ### RS-170
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| − | ### NTSC
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| − | ### VGA, SVGA, HDTV
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| − | ### GPUs
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| − | #### Example: NVIDIA FERMI CUDA GPU Architecture
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| − | #### Example: Simple GPU for the 1-bus SRC
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| − | ## Hard Disks
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| − | # Advanced Topics
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| − | ## Pipelining
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| − | ### General Principles
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| − | ### Example: Pipelined SRC (w/VHDL Model)*
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| − | ### Flynn Limit
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| − | ## Instruction Level Parallelism
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| − | ### Superscalar Processors
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| − | #### General Principles
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| − | #### Example: Intel Pentium (1st Superscalar X86 CPU)
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| − | #### Example: AMD K7 (9-issue, Speculative Out-of-Order Execution, etc.)
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| − | ### VLIW Machines
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| − | #### General Principles
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| − | #### Example: IBM VLIW Prototype
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| − | #### Example: Intel Itanium/EPIC
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| − | ## Microprogramming
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| − | ### General Principles
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| − | ### Example: Microprogrammed SRC (w/VHDL Model)*
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| − | ## Code Morphing
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| − | ### Example: Transmeta Crusoe
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| − | ## Extending the Address Space
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| − | ### 16- to 32-bit: Intel 80386
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| − | ### 32- to 64-bit: AMD Hammer vs Intel Itanium
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| − | ## Multicore CPUs
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| − | ### Amdahl's Law
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| − | ### Symetric Multiprocessing (SMP)
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| − | #### Example: Intel i7-980X
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| − | ### Cache Coherency
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| − | ####MESI (Illinois Protocol)
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| − | ####MESIF (Intel starting with Nahelem)
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| − | ####MOESI (AMD starting with AMD64)
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| − | ### Simultaneous Multi-Threading (SMT)
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| − | #### Intel Hyperthreading
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| − | #### Sun Microsystems Barrel Processors
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| − | ### OpenMP
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