Difference between revisions of "Lecture Notes"
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File:EPROM Example.sch|ExpressPCB | File:EPROM Example.sch|ExpressPCB | ||
File:SRAM Example.pdf|SRC SRAM Example | File:SRAM Example.pdf|SRC SRAM Example | ||
| − | File:DRAM Example.pdf|SRC DRAM Example | + | File:DRAM_Moore_Example.pdf|SRC DRAM (Moore FSM) Example |
| − | File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh | + | File:DRAM Example.pdf|SRC DRAM (Mealy FSM) Example |
| + | File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh (Mealy FSM) | ||
File:Cache Example.pdf|SRC Cache Example | File:Cache Example.pdf|SRC Cache Example | ||
</gallery> | </gallery> | ||
Revision as of 15:09, 7 October 2014
- Introduction
Introduction
Errata
Appendix A
Appendix C
SRC Reference
- Chapter 1
Chapter 1
- Chapter 2
Chapter 2
SRC RTN
- Chapter 3
Chapter 3
- Chapter 4
Chapter 4
One-Bus SRC Block Diagrams
One-Bus SRC RTN
One-Bus SRC VHDL
SRC VHDL Tutorial
Xilinx Virtex 6 Configurable Logic Block User Guide
SRC User Constraint File
SRC Synthesis Report
SRC Place-and-Route Report
SRC Pinout Report
SRC Timing (Trace) Report
SRC Datasheet
One-Bus SRC with DCM VHDL
SRC with DCM Datasheet
One-Mux SRC Block Diagrams
Two-Bus SRC
Three-Bus SRC
Standard Cell SRC?
- Chapter 5
Chapter 5
Table 5.1
Corrected Figure 5.15
Pipelined SRC
Pipelined SRC VHDL Source (Instructor Only)
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
Microprogrammed SRC Control
Microprogrammed SRC Control Store
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
AMD K7 Presentation
AMD Hammer Presentation
VLIW Notes
Intel Itanium
Intel Itanium Software Developer's Guide
Transmeta Crusoe White Paper
HP Transmeta Crusoe Laptop
Intel PII System
Intel Core I7-980X Product Brief
Intel Core I7-980X Diemap
Illinois Protocol
Hyper-Threaded SRC Concept
SPARC T5
Intel Xeon Phi
Expressing Parallelism
Where to Go From Here
CPU History
The First Superscalar X86 CPU: The P5
Original AMD Athlon on Wikipedia
HP TC 1000 Crusoe-Based Tablet PC
Thread (Computing) on Wikipedia
Simultaneous Multithreading on Wikipedia
SPARC T1 "Multi-threaded" CPU on Wikipedia
SPARC T3 "Multi-threaded" CPU on Wikipedia
History of Supercomputing on Wikipedia
Cluster Computing on Wikipedia
- Chapter 6
Chapter 6
Supplement 1
Supplement 2
Supplement 3
- Chapter 7
Chapter 7
SRC EPROM Example
ExpressPCB
SRC SRAM Example
SRC DRAM (Moore FSM) Example
SRC DRAM (Mealy FSM) Example
SRC DRAM Example W/Refresh (Mealy FSM)
SRC Cache Example
- Chapter 8
Chapter 8
Stereo Card Example
Stereo Card VHDL
IN & OUT RTN
Metastability Lecture
Metastability 1
Metastability 2
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
Bus-Master Stereo SRC Audio Card VHDL
THREE-SLOT MULTI-MASTER SRC MOTHERBOARD
PCI
Intel PCI Chipset Evolution
Parallel vs. Serial Buses
Reflection Example
PCIe
Coding Theory 001
Hamming Codes
State Equal Output Moore Example
- Chapter 9
Chapter 9
NTSC Video
Video Example
NVIDIA FERMI
Video Chapter
- Chapter 10
Chapter 10
RS232 Examples
MAX232 IC
National DS92LV16 SERDES
USB 2.0
VHDL Lecture
