Difference between revisions of "Lecture Notes"
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File:CPU_History.pdf|CPU History | File:CPU_History.pdf|CPU History | ||
</gallery> | </gallery> | ||
+ | [http://en.wikipedia.org/wiki/Intel_Pentium_4 Intel P4 Netburst CPU] | ||
[http://en.wikipedia.org/wiki/Microcode Microcode] | [http://en.wikipedia.org/wiki/Microcode Microcode] | ||
− | + | [http://en.wikipedia.org/wiki/Intel_P5 The First Superscalar X86 CPU: The P5] | |
+ | [http://www.en.wikipedia.org/wiki/Athlon Original AMD Athlon on Wikipedia] | ||
[http://en.wikipedia.org/wiki/VLIW VLIW on Wikipedia] | [http://en.wikipedia.org/wiki/VLIW VLIW on Wikipedia] | ||
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[http://www.research.ibm.com/vliw/ VLIW at IBM] | [http://www.research.ibm.com/vliw/ VLIW at IBM] | ||
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[http://www.research.ibm.com/vliw/Images/alltree.gif VLIW Tree-Instruction Example] | [http://www.research.ibm.com/vliw/Images/alltree.gif VLIW Tree-Instruction Example] | ||
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[http://www.en.wikipedia.org/wiki/Itanium Intel Itanium] | [http://www.en.wikipedia.org/wiki/Itanium Intel Itanium] | ||
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[http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&taskId=120&prodSeriesId=307008&prodTypeId=321957&objectID=c00351475 HP TC 1000 Crusoe-Based Tablet PC] | [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&taskId=120&prodSeriesId=307008&prodTypeId=321957&objectID=c00351475 HP TC 1000 Crusoe-Based Tablet PC] | ||
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[http://en.wikipedia.org/wiki/UltraSPARC_T1 SPARC T1 "Multi-threaded" CPU] | [http://en.wikipedia.org/wiki/UltraSPARC_T1 SPARC T1 "Multi-threaded" CPU] | ||
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[http://en.wikipedia.org/wiki/SPARC_T3 SPARC T3 "Multi-threaded" CPU] | [http://en.wikipedia.org/wiki/SPARC_T3 SPARC T3 "Multi-threaded" CPU] | ||
Revision as of 16:26, 19 November 2013
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
Intel P4 Netburst CPU Microcode The First Superscalar X86 CPU: The P5 Original AMD Athlon on Wikipedia VLIW on Wikipedia VLIW at IBM VLIW Tree-Instruction Example Intel Itanium HP TC 1000 Crusoe-Based Tablet PC SPARC T1 "Multi-threaded" CPU SPARC T3 "Multi-threaded" CPU
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
- State Equal Output Moore Example.pdf
State Equal Output Moore Example