Difference between revisions of "Lecture Notes"
| Line 48: | Line 48: | ||
[http://www.en.wikipedia.org/wiki/Itanium| Intel Itanium] | [http://www.en.wikipedia.org/wiki/Itanium| Intel Itanium] | ||
| + | |||
| + | <gallery caption="Chapter 6"> | ||
| + | File:Ch6CSDA.pdf|Chapter 6 | ||
| + | File:Carry Lookahead.pdf|Supplement 1 | ||
| + | File:Chapter 6 Math Lectures.pdf|Supplement 2 | ||
| + | File:Multiplication.pdf|Supplement 3 | ||
| + | </gallery> | ||
| + | |||
| + | <gallery caption="Chapter 7"> | ||
| + | File:Ch7CSDA.pdf|Chapter 7 | ||
| + | File:Eprom Example.pdf|SRC EPROM Example | ||
| + | File:EPROM Example.sch|ExpressPCB | ||
| + | File:SRAM Example.pdf|SRC SRAM Example | ||
| + | File:DRAM Example.pdf|SRC DRAM Example | ||
| + | File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh | ||
| + | File:Cache Example.pdf|SRC Cache Example | ||
| + | </gallery> | ||
| + | [http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html| Intel i7 Cache Article] | ||
| + | |||
| + | <gallery caption="Chapter 8"> | ||
| + | File:Ch8CSDA.pdf|Chapter 8 | ||
| + | File:stereo.pdf|Stereo Card Example | ||
| + | File:stereo.zip|Stereo Card VHDL | ||
| + | File:IN OUT RTN.pdf|IN & OUT RTN | ||
| + | File:Metastability Lecture.pdf|Metastability Lecture | ||
| + | File:Paper1.pdf|Metastability 1 | ||
| + | File:Paper2.pdf|Metastability 2 | ||
| + | File:multimastersrcvhdl.zip|Multi-Master SRC VHDL | ||
| + | File:PCI Lecture.pdf|PCI | ||
| + | File:Reflection Lecture.pdf|Parallel vs. Serial Buses | ||
| + | File:PCIe Lecture.pdf|PCIe | ||
| + | File:Coding Theory 001.pdf|Coding Theory 001 | ||
| + | File:Hamming Code Example With Odd Parity.pdf|Hamming Codes | ||
| + | File:State Equal Output Moore Example.pdf|State Equal Output Moore Example | ||
| + | </gallery> | ||
Revision as of 18:16, 1 December 2009
- Introduction
Introduction
Errata
Appendix A
Appendix C
SRC Reference
- Chapter 1
Chapter 1
- Chapter 2
Chapter 2
- Chapter 3
Chapter 3
- Chapter 4
- Ch4CSDA.pdf
Chapter 4
One-Bus SRC Block Diagrams
One-Bus SRC RTN
One-Bus SRC VHDL
- Testbench.pdf
One-Bus SRC Simulation
One-Mux SRC Block Diagrams
- Synthesis Report.pdf
XC3S500E-4 SRC Synthesis Report
- Place&Route.pdf
XC3S500E-4 SRC Place and Route Report
- Timing Report.pdf
XC3S500E-4 SRC Timing Report
Two-Bus SRC
- Chapter 5
Chapter 5
Pipelined SRC
VLIW Notes
AMD K7 Presentation
AMD Hammer Presentation
Transmeta Crusoe White Paper
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
Original AMD Athlon on Wikipedia
- Chapter 6
Chapter 6
Supplement 1
Supplement 2
Supplement 3
- Chapter 7
Chapter 7
- Eprom Example.pdf
SRC EPROM Example
ExpressPCB
SRC SRAM Example
SRC DRAM Example
SRC DRAM Example W/Refresh
SRC Cache Example
- Chapter 8
Chapter 8
Stereo Card Example
Stereo Card VHDL
IN & OUT RTN
Metastability Lecture
Metastability 1
Metastability 2
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
PCI
Parallel vs. Serial Buses
PCIe
Coding Theory 001
Hamming Codes
- State Equal Output Moore Example.pdf
State Equal Output Moore Example
