Difference between revisions of "Lecture Notes"
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File:DRAM_Example_Datapath.pdf|DRAM Example Datapath | File:DRAM_Example_Datapath.pdf|DRAM Example Datapath | ||
File:DRAM_Moore_Example.pdf|SRC DRAM (Moore FSM) Example | File:DRAM_Moore_Example.pdf|SRC DRAM (Moore FSM) Example | ||
+ | File:DRAM_Moore_Refresh_Example.pdf|SRC DRAM Example W/Refresh (Moore FSM) | ||
File:DRAM Example.pdf|SRC DRAM (Mealy FSM) Example | File:DRAM Example.pdf|SRC DRAM (Mealy FSM) Example | ||
File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh (Mealy FSM) | File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh (Mealy FSM) |
Revision as of 23:01, 12 October 2016
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
The Intel 8086/8088: The Original IBM PC CPU
The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286
The First 32-bit X86 CPU: The Intel 80386
The First Tightly Pipelined X86 CPU: The Intel 80486
The First Superscalar X86 CPU: The Intel P5
The First 64-bit X86 CPU: The AMD Opteron
Original AMD Athlon on Wikipedia
The Father of VLIW: Josh Fisher
Intel's First VLIW CPU (Failure): The i860
How the Itanium Killed the Computer Industry
HP and Intel Effectively Kill off Itanium
HP TC 1000 Crusoe-Based Tablet PC
Thread (Computing) on Wikipedia
Simultaneous Multithreading on Wikipedia
SPARC T1 "Multi-threaded" CPU on Wikipedia
SPARC T3 "Multi-threaded" CPU on Wikipedia
Implementing Scalable Atomic Locks for Multi-Core Intel® EM64T and IA32 Architectures
History of Supercomputing on Wikipedia
Cluster Computing on Wikipedia
Hennessy and Patterson on the Intel i7
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
- 2-Bit Flash ADC.png
2-Bit Pipelined Flash ADC