Lecture Notes

• Introduction
• 

  Introduction

• 

  Errata

• 

  Appendix A

• 

  Appendix C

• 

  SRC Reference

• Chapter 1
• 

  Chapter 1

• Chapter 2
• 

  Chapter 2

• 

  SRC RTN

• Chapter 3
• 

  Chapter 3

• Chapter 4
• 

  Chapter 4

• 

  Displacement-Based Addressing

• 

  One-Bus SRC Block Diagrams

• 

  One-Bus SRC RTN

• 

  One-Bus SRC VHDL

• 

  SRC VHDL Tutorial

• 

  Xilinx Virtex 6 Configurable Logic Block User Guide

• 

  SRC User Constraint File

• 

  SRC Synthesis Report

• 

  SRC Place-and-Route Report

• 

  SRC Pinout Report

• 

  SRC Timing (Trace) Report

• 

  SRC Datasheet

• 

  One-Bus SRC with DCM VHDL

• 

  SRC with DCM Datasheet

• 

  One-Mux SRC Block Diagrams

• 

  Two-Bus SRC

• 

  Three-Bus SRC

• 

  Standard Cell SRC?

• Chapter 5
• 

  Chapter 5

• 

  Table 5.1

• 

  Corrected Figure 5.15

• 

  Pipelined SRC

• 

  Pipelined SRC VHDL Source (Instructor Only)

• Microprogrammed SRC Control Unit.pdf

  Microprogrammed SRC

• 

  Microprogrammed SRC Control

• 

  Microprogrammed SRC Control Store

• Microcodedsrcvhdl.zip

  One-Bus Microcoded SRC VHDL

• 

  Microsoft Windows (TM) Version History

• 

  Microsoft Windows for Workgroups(TM) Version History

• 

  AMD K7 Presentation

• 

  AMD Hammer Presentation

• 

  VLIW Notes

• 

  Fisher Paper 1

• 

  Fisher Paper 2

• 

  Intel Itanium

• 

  Intel Itanium Software Developer's Guide

• 

  Transmeta Crusoe White Paper

• 

  HP Transmeta Crusoe Laptop

• 

  Intel PII System

• 

  Intel 440FX Chipset

• 

  Intel 440LX Chipset

• 

  Intel Core I7-980X Product Brief

• 

  Intel Core I7-980X Diemap

• 

  Illinois Protocol

• 

  Hyper-Threaded SRC Concept

• 

  SPARC T5

• 

  Intel Xeon Phi

• 

  Expressing Parallelism

• 

  Where to Go From Here

• 

  CPU History

Intel P4 Netburst CPU

Microcode

The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286

The First 32-bit X86 CPU: The Intel 80386

The First Tightly Pipelined X86 CPU: The Intel 80486

The First Superscalar X86 CPU: The Intel P5

The First 64-bit X86 CPU: The AMD Opteron

Original AMD Athlon on Wikipedia

VLIW on Wikipedia

The Father of VLIW: Josh Fisher

VLIW at IBM

VLIW Tree-Instruction Example

Intel's First VLIW CPU (Failure): The i860

Intel Itanium

HP TC 1000 Crusoe-Based Tablet PC

SMP on Wikipedia

Cache Coherence on Wikipedia

Thread (Computing) on Wikipedia

Simultaneous Multithreading on Wikipedia

Hyper-Threading on Wikipedia

SPARC T1 "Multi-threaded" CPU on Wikipedia

SPARC T3 "Multi-threaded" CPU on Wikipedia

History of Supercomputing on Wikipedia

Cluster Computing on Wikipedia

Intel Xeon Phi

• Chapter 6
• 

  Chapter 6

• 

  Supplement 1

• 

  Supplement 2

• 

  Supplement 3

• Chapter 7
• 

  Chapter 7

• 

  SRC EPROM Example

• 

  ExpressPCB EPROM Schematic

• 

  SRC SRAM Example

• 

  ExpressPCB SRAM Schematic

• 

  DRAM Example Datapath

• 

  SRC DRAM (Moore FSM) Example

• 

  SRC DRAM (Mealy FSM) Example

• 

  SRC DRAM Example W/Refresh (Mealy FSM)

• 

  DRAM Types

• 

  SRC Cache Example

• 

  SRC Cache Datapath

• 

  Virtual Memory Concepts

Hennessy and Patterson on the Intel i7

Intel i7 Cache Article

• Chapter 8
• 

  Chapter 8

• 

  Stereo Card Example

• 

  Stereo Card VHDL

• 

  IN & OUT RTN

• 

  Metastability Lecture

• 

  Metastability 1

• 

  Metastability 2

• Multimastersrcvhdl.zip

  Multi-Master SRC VHDL

• 

  Bus-Master Stereo SRC Audio Card VHDL

• 

  THREE-SLOT MULTI-MASTER SRC MOTHERBOARD

• 

  PCI

• 

  Intel PCI Chipset Evolution

• 

  Reflection Lecture (Parallel vs. Serial Buses)

• 

  LTSPICE IV Quick Tutorial

• 

  Reflection Example

• 

  PCIe

• 

  Coding Theory 001

• 

  Hamming Codes

• 

  State Equal Output Moore Example

• 

  IBM 5160 Technical Reference

• Chapter 9
• 

  Chapter 9

• 

  NTSC Video

• 

  Video Example

• 

  NVIDIA FERMI

• 

  Video Chapter

• Chapter 10
• 

  Chapter 10

• 

  RS232 Examples

• 

  MAX232 IC

• 

  National DS92LV16 SERDES

• 

  USB 2.0

• 

  VHDL Lecture