Difference between revisions of "Lecture Notes"

From CSE362 Wiki
Jump to navigationJump to search
Line 56: Line 56:
 
File:MPF_Hammer_Presentation.pdf|AMD Hammer Presentation
 
File:MPF_Hammer_Presentation.pdf|AMD Hammer Presentation
 
File:VLIW.pdf|VLIW Notes
 
File:VLIW.pdf|VLIW Notes
 +
File:Fisher_Paper_1.pdf|Fisher Paper 1
 +
File:Fisher_Paper_2.pdf|Fisher Paper 2
 
File:Itanium.ua_ovw.pdf|Intel Itanium
 
File:Itanium.ua_ovw.pdf|Intel Itanium
 
File:Itanium-architecture-vol-1-2-3-4-reference-set-manual.pdf|Intel Itanium Software Developer's Guide
 
File:Itanium-architecture-vol-1-2-3-4-reference-set-manual.pdf|Intel Itanium Software Developer's Guide

Revision as of 16:49, 20 November 2014

Intel P4 Netburst CPU

Microcode

The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286

The First 32-bit X86 CPU: The Intel 80386

The First Tightly Pipelined X86 CPU: The Intel 80486

The First Superscalar X86 CPU: The Intel P5

The First 64-bit X86 CPU: The AMD Opteron

Original AMD Athlon on Wikipedia

VLIW on Wikipedia

The Father of VLIW: Josh Fisher

VLIW at IBM

VLIW Tree-Instruction Example

Intel's First VLIW CPU (Failure): The i860

Intel Itanium

HP TC 1000 Crusoe-Based Tablet PC

SMP on Wikipedia

Cache Coherence on Wikipedia

Thread (Computing) on Wikipedia

Simultaneous Multithreading on Wikipedia

Hyper-Threading on Wikipedia

SPARC T1 "Multi-threaded" CPU on Wikipedia

SPARC T3 "Multi-threaded" CPU on Wikipedia

History of Supercomputing on Wikipedia

Cluster Computing on Wikipedia

Intel Xeon Phi

Hennessy and Patterson on the Intel i7

Intel i7 Cache Article

IBM 5160 Technical Reference