Difference between revisions of "Lecture Notes"
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File:I7-980X_Diemap.jpg|Intel Core I7-980X Diemap | File:I7-980X_Diemap.jpg|Intel Core I7-980X Diemap | ||
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[http://en.wikipedia.org/wiki/Intel_P5 The First Superscalar X86 CPU: The P5] | [http://en.wikipedia.org/wiki/Intel_P5 The First Superscalar X86 CPU: The P5] | ||
Revision as of 15:30, 7 December 2010
- Introduction
Introduction
Errata
Appendix A
Appendix C
SRC Reference
- Chapter 1
Chapter 1
- Chapter 2
Chapter 2
- Chapter 3
Chapter 3
- Chapter 4
Chapter 4
One-Bus SRC Block Diagrams
One-Bus SRC RTN
One-Bus SRC VHDL
- Testbench.pdf
One-Bus SRC Simulation
One-Mux SRC Block Diagrams
- Synthesis Report.pdf
XC3S500E-4 SRC Synthesis Report
- Place&Route.pdf
XC3S500E-4 SRC Place and Route Report
- Timing Report.pdf
XC3S500E-4 SRC Timing Report
Two-Bus SRC
- Chapter 5
Chapter 5
Table 5.1
Pipelined SRC
VLIW Notes
AMD K7 Presentation
AMD Hammer Presentation
Transmeta Crusoe White Paper
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
Microprogrammed SRC Control
Microprogrammed SRC Control Store
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
Intel Core I7-980X Product Brief
Intel Core I7-980X Diemap
Expressing Parallelism
Where to Go From Here
The First Superscalar X86 CPU: The P5
Original AMD Athlon on Wikipedia
HP TC 1000 Crusoe-Based Tablet PC
- Chapter 6
Chapter 6
Supplement 1
Supplement 2
Supplement 3
- Chapter 7
Chapter 7
- Eprom Example.pdf
SRC EPROM Example
ExpressPCB
SRC SRAM Example
SRC DRAM Example
SRC DRAM Example W/Refresh
SRC Cache Example
- Chapter 8
Chapter 8
Stereo Card Example
Stereo Card VHDL
IN & OUT RTN
Metastability Lecture
Metastability 1
Metastability 2
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
Bus-Master Stereo SRC Audio Card VHDL
PCI
Parallel vs. Serial Buses
PCIe
Coding Theory 001
Hamming Codes
- State Equal Output Moore Example.pdf
State Equal Output Moore Example
- Chapter 9
Chapter 9
NTSC Video
Video Example
NVIDIA FERMI
Video Chapter
- Chapter 10
Chapter 10
RS232 Examples
National DS92LV16 SERDES
USB 2.0
VHDL Lecture
