Difference between revisions of "Lecture Notes"
From CSE362 Wiki
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File:Microprogrammed SRC Control Unit.pdf|Microprogrammed SRC | File:Microprogrammed SRC Control Unit.pdf|Microprogrammed SRC | ||
</gallery> | </gallery> | ||
− | [http://www.research.ibm.com/vliw/ | + | [http://www.research.ibm.com/vliw/ VLIW at IBM] |
− | [http://www.research.ibm.com/vliw/Images/alltree.gif | + | [http://www.research.ibm.com/vliw/Images/alltree.gif VLIW Tree-Instruction Example] |
− | [http://www.en.wikipedia.org/wiki/Athlon | + | [http://www.en.wikipedia.org/wiki/Athlon Original AMD Athlon on Wikipedia] |
− | [http://www.en.wikipedia.org/wiki/Itanium | + | [http://www.en.wikipedia.org/wiki/Itanium Intel Itanium] |
<gallery caption="Chapter 6"> | <gallery caption="Chapter 6"> | ||
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File:Cache Example.pdf|SRC Cache Example | File:Cache Example.pdf|SRC Cache Example | ||
</gallery> | </gallery> | ||
− | [http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html | + | [http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html Intel i7 Cache Article] |
<gallery caption="Chapter 8"> | <gallery caption="Chapter 8"> |
Revision as of 15:48, 9 November 2010
- Testbench.pdf
One-Bus SRC Simulation
- Synthesis Report.pdf
XC3S500E-4 SRC Synthesis Report
- Place&Route.pdf
XC3S500E-4 SRC Place and Route Report
- Timing Report.pdf
XC3S500E-4 SRC Timing Report
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
Original AMD Athlon on Wikipedia
- Eprom Example.pdf
SRC EPROM Example
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
- State Equal Output Moore Example.pdf
State Equal Output Moore Example