Difference between revisions of "General Information"

From CSE362 Wiki
Jump to navigationJump to search
Line 1: Line 1:
Instructor, William D. Richard, Ph.D., Jolley Hall 538, 314-935-4676, wdr@wustl.edu
+
<strong>Instructor:</strong> William D. Richard, Ph.D., Jolley Hall 538, 314-935-4676, wdr@wustl.edu
  
Office Hours: Monday and Wednesday, 10-11:30 a.m. or by appointment
+
<strong>Office Hours:</strong> Tuesday/Thursday 9:00 - 11:00 a.m. or by appointment
  
Course Web Page: http://classes.engineering.wustl.edu/cse362
+
<strong>Course Web Page:</strong> http://classes.engineering.wustl.edu/permanant/cse260m/index.php/Main_Page
  
Text: Computer Systems Design and Architecture, 2nd Edition, Heuring and Jordan, Addisson Wesley, 2004, ISBN: 0-13-048440-7
+
<strong>Student Resources Web Page:</strong> http://wps.pearsoned.com/ecs_mano_lcdf_5/248/63706/16308896.cw/index.html
  
Class Meeting: Tuesday and Thursday, 11:30 a.m. - 1:00 p.m., Location: TBD
+
<strong>Text:</strong> Logic and Computer Design Fundamentals (5th Edition), Mano/Kim/Martin, Prentice Hall, 2016, ISBN 0-13-376063-4.
  
Exam #1: TBD
+
<strong>Class Meeting:</strong> Mondays and Wednesdays, 2:30 - 4:00 p.m., Location: TBD
  
Exam #2: TBD
+
<strong>Exam #1:</strong> October 2, 2017
  
Exam #3: TBD
+
<strong>Exam #2:</strong> November 6, 2017
  
<strong>Grading:</strong> Three exams, 33.3% each.
+
<strong>Exam #3:</strong> December 6, 2017
 +
 
 +
<strong>GRADING:</strong> Exam 1: 33 1&frasl;3%; Exam 2: 33 1&frasl;3%; Exam 3: 33 1&frasl;3%
  
 
{| class="wikitable" style="text-align: center; color: green;"
 
{| class="wikitable" style="text-align: center; color: green;"
Line 70: Line 72:
 
|}
 
|}
  
Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded by the instructor and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity.
+
<strong>HOMEWORK:</strong> Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity.
 +
 
 +
<strong>LABORITORIES:</strong> Three laboratories will be assigned during the semester. Laboratories must be done on an individual basis, and students collaborating with or submitting VHDL or bit files done by someone else for grading will be considered to have violated the course policy on academic integrity.
 +
 
 +
<strong>ATTENDANCE:</strong> Attendance is required. Students missing seven (7) or more lectures during the semester will be assigned a course grade of "F." Since family and medical emergencies are possible, this should be taken into consideration by students electing to miss classes for "non-emergency" reasons. No exceptions will be made.

Revision as of 13:22, 10 May 2017

Instructor: William D. Richard, Ph.D., Jolley Hall 538, 314-935-4676, wdr@wustl.edu

Office Hours: Tuesday/Thursday 9:00 - 11:00 a.m. or by appointment

Course Web Page: http://classes.engineering.wustl.edu/permanant/cse260m/index.php/Main_Page

Student Resources Web Page: http://wps.pearsoned.com/ecs_mano_lcdf_5/248/63706/16308896.cw/index.html

Text: Logic and Computer Design Fundamentals (5th Edition), Mano/Kim/Martin, Prentice Hall, 2016, ISBN 0-13-376063-4.

Class Meeting: Mondays and Wednesdays, 2:30 - 4:00 p.m., Location: TBD

Exam #1: October 2, 2017

Exam #2: November 6, 2017

Exam #3: December 6, 2017

GRADING: Exam 1: 33 1⁄3%; Exam 2: 33 1⁄3%; Exam 3: 33 1⁄3%

SCORE GRADE OPTION PASS/FAIL OPTION
97 A+ Pass
93 A
90 A-
87 B+
93 B
80 B-
77 C+
73 C
70 C-
60 D Fail
0 F

HOMEWORK: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity.

LABORITORIES: Three laboratories will be assigned during the semester. Laboratories must be done on an individual basis, and students collaborating with or submitting VHDL or bit files done by someone else for grading will be considered to have violated the course policy on academic integrity.

ATTENDANCE: Attendance is required. Students missing seven (7) or more lectures during the semester will be assigned a course grade of "F." Since family and medical emergencies are possible, this should be taken into consideration by students electing to miss classes for "non-emergency" reasons. No exceptions will be made.