Difference between revisions of "Lecture Notes"

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File:Table_5P1.pdf|Table 5.1
 
File:Table_5P1.pdf|Table 5.1
 
File:Corrected_Figure_5.15.pdf|Corrected Figure 5.15
 
File:Corrected_Figure_5.15.pdf|Corrected Figure 5.15
File:BasicPipelinedSRC.pdf
+
File:BasicPipelinedSRC.pdf|Basic Pipelined SRC
 
File:Pipelined SRC.pdf|Pipelined SRC
 
File:Pipelined SRC.pdf|Pipelined SRC
 
File:src.pdf|Pipelined SRC VHDL Source (Instructor Only)
 
File:src.pdf|Pipelined SRC VHDL Source (Instructor Only)

Revision as of 15:42, 12 November 2015

Intel P4 Netburst CPU

Microcode

The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286

The First 32-bit X86 CPU: The Intel 80386

The First Tightly Pipelined X86 CPU: The Intel 80486

The First Superscalar X86 CPU: The Intel P5

The First 64-bit X86 CPU: The AMD Opteron

Original AMD Athlon on Wikipedia

VLIW on Wikipedia

The Father of VLIW: Josh Fisher

VLIW at IBM

VLIW Tree-Instruction Example

Intel's First VLIW CPU (Failure): The i860

Intel Itanium

HP TC 1000 Crusoe-Based Tablet PC

SMP on Wikipedia

Cache Coherence on Wikipedia

Thread (Computing) on Wikipedia

Simultaneous Multithreading on Wikipedia

Hyper-Threading on Wikipedia

SPARC T1 "Multi-threaded" CPU on Wikipedia

SPARC T3 "Multi-threaded" CPU on Wikipedia

History of Supercomputing on Wikipedia

Cluster Computing on Wikipedia

Intel Xeon Phi

Hennessy and Patterson on the Intel i7

Intel i7 Cache Article