Difference between revisions of "Lecture Notes"

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<gallery caption="Chapter 4">
 
<gallery caption="Chapter 4">
 
File:Ch4WDR.pdf|Chapter 4
 
File:Ch4WDR.pdf|Chapter 4
 +
File:DISPLACEMENT.pdf|Displacement-Based Addressing
 
File:1-Bus Block Diagrams.pdf|One-Bus SRC Block Diagrams
 
File:1-Bus Block Diagrams.pdf|One-Bus SRC Block Diagrams
 
File:1busrtn.pdf|One-Bus SRC RTN
 
File:1busrtn.pdf|One-Bus SRC RTN

Revision as of 20:43, 18 September 2015

Intel P4 Netburst CPU

Microcode

The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286

The First 32-bit X86 CPU: The Intel 80386

The First Tightly Pipelined X86 CPU: The Intel 80486

The First Superscalar X86 CPU: The Intel P5

The First 64-bit X86 CPU: The AMD Opteron

Original AMD Athlon on Wikipedia

VLIW on Wikipedia

The Father of VLIW: Josh Fisher

VLIW at IBM

VLIW Tree-Instruction Example

Intel's First VLIW CPU (Failure): The i860

Intel Itanium

HP TC 1000 Crusoe-Based Tablet PC

SMP on Wikipedia

Cache Coherence on Wikipedia

Thread (Computing) on Wikipedia

Simultaneous Multithreading on Wikipedia

Hyper-Threading on Wikipedia

SPARC T1 "Multi-threaded" CPU on Wikipedia

SPARC T3 "Multi-threaded" CPU on Wikipedia

History of Supercomputing on Wikipedia

Cluster Computing on Wikipedia

Intel Xeon Phi

Hennessy and Patterson on the Intel i7

Intel i7 Cache Article

IBM 5160 Technical Reference