Difference between revisions of "Lecture Notes"

From CSE362 Wiki
Jump to navigationJump to search
 
(73 intermediate revisions by the same user not shown)
Line 22: Line 22:
 
<gallery caption="Chapter 4">
 
<gallery caption="Chapter 4">
 
File:Ch4WDR.pdf|Chapter 4
 
File:Ch4WDR.pdf|Chapter 4
 +
File:DISPLACEMENT.pdf|Displacement-Based Addressing
 
File:1-Bus Block Diagrams.pdf|One-Bus SRC Block Diagrams
 
File:1-Bus Block Diagrams.pdf|One-Bus SRC Block Diagrams
 
File:1busrtn.pdf|One-Bus SRC RTN
 
File:1busrtn.pdf|One-Bus SRC RTN
 
File:srcvhdl.zip|One-Bus SRC VHDL
 
File:srcvhdl.zip|One-Bus SRC VHDL
 
File:SRC_VHDL_Tutorial.pdf|SRC VHDL Tutorial
 
File:SRC_VHDL_Tutorial.pdf|SRC VHDL Tutorial
 +
File:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem
 
File:Ug364.pdf|Xilinx Virtex 6 Configurable Logic Block User Guide
 
File:Ug364.pdf|Xilinx Virtex 6 Configurable Logic Block User Guide
 +
File:SRCUCF.pdf|SRC User Constraint File
 
File:SRCSYR.pdf|SRC Synthesis Report
 
File:SRCSYR.pdf|SRC Synthesis Report
 
File:SRCPAR.pdf|SRC Place-and-Route Report
 
File:SRCPAR.pdf|SRC Place-and-Route Report
 +
File:SRCPIN.pdf|SRC Pinout Report
 
File:SRCTWR.pdf|SRC Timing (Trace) Report
 
File:SRCTWR.pdf|SRC Timing (Trace) Report
 +
File:SRCDATASHEET.pdf|SRC Datasheet
 +
File:SRC_DCM_VHDL.pdf|One-Bus SRC with DCM VHDL
 +
File:SRCDCMDATASHEET.pdf|SRC with DCM Datasheet
 
File:1-Mux Block Diagrams.pdf|One-Mux SRC Block Diagrams
 
File:1-Mux Block Diagrams.pdf|One-Mux SRC Block Diagrams
 
File:Two Bus SRC.pdf|Two-Bus SRC
 
File:Two Bus SRC.pdf|Two-Bus SRC
Line 38: Line 45:
 
<gallery caption="Chapter 5">
 
<gallery caption="Chapter 5">
 
File:Ch5CSDA.pdf|Chapter 5
 
File:Ch5CSDA.pdf|Chapter 5
 +
File:RISC.pdf|Patterson/Ditzel ACM SIGARCH Computer Architecture News Article on RISC
 
File:Table_5P1.pdf|Table 5.1
 
File:Table_5P1.pdf|Table 5.1
 
File:Corrected_Figure_5.15.pdf|Corrected Figure 5.15
 
File:Corrected_Figure_5.15.pdf|Corrected Figure 5.15
 +
File:BasicPipelinedSRC.pdf|Basic Pipelined SRC
 
File:Pipelined SRC.pdf|Pipelined SRC
 
File:Pipelined SRC.pdf|Pipelined SRC
 
File:src.pdf|Pipelined SRC VHDL Source (Instructor Only)
 
File:src.pdf|Pipelined SRC VHDL Source (Instructor Only)
Line 46: Line 55:
 
File:Controlstore.pdf|Microprogrammed SRC Control Store
 
File:Controlstore.pdf|Microprogrammed SRC Control Store
 
File:Microcodedsrcvhdl.zip|One-Bus Microcoded SRC VHDL
 
File:Microcodedsrcvhdl.zip|One-Bus Microcoded SRC VHDL
 +
File:Windows_Version_History.pdf | Microsoft Windows (TM) Version History
 +
File:Windows_for_Workgroups_Version_History.pdf | Microsoft Windows for Workgroups(TM) Version History
 
File:k7pres.pdf|AMD K7 Presentation
 
File:k7pres.pdf|AMD K7 Presentation
 
File:MPF_Hammer_Presentation.pdf|AMD Hammer Presentation
 
File:MPF_Hammer_Presentation.pdf|AMD Hammer Presentation
 
File:VLIW.pdf|VLIW Notes
 
File:VLIW.pdf|VLIW Notes
 +
File:Fisher_Paper_1.pdf|Fisher Paper 1
 +
File:Fisher_Paper_2.pdf|Fisher Paper 2
 
File:Itanium.ua_ovw.pdf|Intel Itanium
 
File:Itanium.ua_ovw.pdf|Intel Itanium
 
File:Itanium-architecture-vol-1-2-3-4-reference-set-manual.pdf|Intel Itanium Software Developer's Guide
 
File:Itanium-architecture-vol-1-2-3-4-reference-set-manual.pdf|Intel Itanium Software Developer's Guide
 
File:paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper
 
File:paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper
 +
File:transmeta.pdf|IEEE Spectrum Article on Transmeta
 
File:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop
 
File:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop
 +
File:Intel_PII_System.JPG|Intel PII MESI System (Circa 1998)
 +
File:29054901-1.pdf|Intel 440FX Pentium Pro Chipset
 +
File:24365703-1.pdf|Intel Pentium II Datasheet
 +
File:29056402.pdf|Intel 440LX Pentium II Chipset
 
File:Intel_Core_i7-980X_Product_Brief.pdf|Intel Core I7-980X Product Brief
 
File:Intel_Core_i7-980X_Product_Brief.pdf|Intel Core I7-980X Product Brief
 
File:I7-980X_Diemap.jpg|Intel Core I7-980X Diemap
 
File:I7-980X_Diemap.jpg|Intel Core I7-980X Diemap
−
File:Papamarcos.isca84.pdf|Illinois Protocol
+
File:MSI_Protocol.pdf|MSI Protocol
 +
File:Papamarcos.isca84.pdf|Illinois (MESI) Protocol
 
File:Hyperthreaded_SRC_Concept.pdf|Hyper-Threaded SRC Concept
 
File:Hyperthreaded_SRC_Concept.pdf|Hyper-Threaded SRC Concept
 +
File:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5
 +
File:Sparc-m6-processor-ds-2015586.pdf|SPARC M6
 +
File:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi Whitepaper
 +
File:High-performance-xeon-phi-coprocessor-brief.pdf|Intel Xeon Phi
 
File:Expressing_Parallelism.pdf| Expressing Parallelism
 
File:Expressing_Parallelism.pdf| Expressing Parallelism
 
File:Where_To_Go_From_Here.pdf| Where to Go From Here
 
File:Where_To_Go_From_Here.pdf| Where to Go From Here
Line 65: Line 88:
 
[http://en.wikipedia.org/wiki/Microcode Microcode]
 
[http://en.wikipedia.org/wiki/Microcode Microcode]
  
−
[http://en.wikipedia.org/wiki/Intel_P5 The First Superscalar X86 CPU: The P5]
+
[https://en.wikipedia.org/wiki/Intel_8086 The Intel 8086/8088: The Original IBM PC CPU]
 +
 
 +
[http://en.m.wikipedia.org/wiki/Intel_80286 The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286]
 +
 
 +
[http://en.m.wikipedia.org/wiki/Intel_80386 The First 32-bit X86 CPU: The Intel 80386]
 +
 
 +
[http://en.m.wikipedia.org/wiki/Intel_80486 The First Tightly Pipelined X86 CPU: The Intel 80486]
 +
 
 +
[https://en.wikipedia.org/wiki/Superscalar_processor Superscalar CPU History]
 +
 
 +
[http://en.wikipedia.org/wiki/Intel_P5 The First Superscalar X86 CPU: The Intel P5]
 +
 
 +
[http://en.m.wikipedia.org/wiki/Opteron The First 64-bit X86 CPU: The AMD Opteron]
  
 
[http://www.en.wikipedia.org/wiki/Athlon Original AMD Athlon on Wikipedia]
 
[http://www.en.wikipedia.org/wiki/Athlon Original AMD Athlon on Wikipedia]
  
 
[http://en.wikipedia.org/wiki/VLIW VLIW on Wikipedia]
 
[http://en.wikipedia.org/wiki/VLIW VLIW on Wikipedia]
 +
 +
[http://en.wikipedia.org/wiki/Josh_Fisher The Father of VLIW: Josh Fisher]
 +
 +
[https://en.wikipedia.org/wiki/Multiflow Multiflow]
  
 
[http://www.research.ibm.com/vliw/ VLIW at IBM]
 
[http://www.research.ibm.com/vliw/ VLIW at IBM]
Line 75: Line 114:
 
[http://www.research.ibm.com/vliw/Images/alltree.gif VLIW Tree-Instruction Example]
 
[http://www.research.ibm.com/vliw/Images/alltree.gif VLIW Tree-Instruction Example]
  
−
[http://www.en.wikipedia.org/wiki/Itanium Intel Itanium]
+
[http://en.wikipedia.org/wiki/Intel_i860 Intel's First VLIW CPU (Failure): The i860]
 +
 
 +
[https://en.wikipedia.org/wiki/Itanium Itanium]
 +
 
 +
[http://www.pcmag.com/article2/0,2817,2339629,00.asp How the Itanium Killed the Computer Industry]
 +
 
 +
[http://semiaccurate.com/2013/02/11/hp-and-intel-effectively-kill-off-itanium/ HP and Intel Effectively Kill off Itanium]
  
−
[http://en.wikipedia.org/wiki/Thread_(computing) Thread (Computing) on Wikipedia]
+
[http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&taskId=120&prodSeriesId=307008&prodTypeId=321957&objectID=c00351475 HP TC 1000 Crusoe-Based Tablet PC]
  
 
[http://en.wikipedia.org/wiki/Symmetric_multiprocessing SMP on Wikipedia]
 
[http://en.wikipedia.org/wiki/Symmetric_multiprocessing SMP on Wikipedia]
 +
 +
[http://en.wikipedia.org/wiki/Cache_coherence Cache Coherence on Wikipedia]
 +
 +
[https://www.linkedin.com/in/markpapamarcos Mark Papmarcos on Linkedin]
 +
 +
[http://en.wikipedia.org/wiki/Thread_(computing) Thread (Computing) on Wikipedia]
  
 
[http://en.wikipedia.org/wiki/Simultaneous_multithreading Simultaneous Multithreading on Wikipedia]
 
[http://en.wikipedia.org/wiki/Simultaneous_multithreading Simultaneous Multithreading on Wikipedia]
Line 85: Line 136:
 
[http://en.wikipedia.org/wiki/Hyperthreading Hyper-Threading on Wikipedia]
 
[http://en.wikipedia.org/wiki/Hyperthreading Hyper-Threading on Wikipedia]
  
−
[http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&taskId=120&prodSeriesId=307008&prodTypeId=321957&objectID=c00351475 HP TC 1000 Crusoe-Based Tablet PC]
+
[http://en.wikipedia.org/wiki/UltraSPARC_T1 SPARC T1 "Multi-threaded" CPU on Wikipedia]
 +
 
 +
[http://en.wikipedia.org/wiki/SPARC_T3 SPARC T3 "Multi-threaded" CPU on Wikipedia]
 +
 
 +
[https://software.intel.com/en-us/articles/implementing-scalable-atomic-locks-for-multi-core-intel-em64t-and-ia32-architectures Implementing Scalable Atomic Locks for Multi-Core Intel® EM64T and IA32 Architectures]
 +
 
 +
[http://en.wikipedia.org/wiki/History_of_supercomputing History of Supercomputing on Wikipedia]
  
−
[http://en.wikipedia.org/wiki/UltraSPARC_T1 SPARC T1 "Multi-threaded" CPU]
+
[http://en.wikipedia.org/wiki/Cluster_%28computing%29 Cluster Computing on Wikipedia]
  
−
[http://en.wikipedia.org/wiki/SPARC_T3 SPARC T3 "Multi-threaded" CPU]
+
[http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html Intel Xeon Phi]
  
 
<gallery caption="Chapter 6">
 
<gallery caption="Chapter 6">
Line 101: Line 158:
 
File:Ch7CSDA.pdf|Chapter 7
 
File:Ch7CSDA.pdf|Chapter 7
 
File:EPROM_Example.pdf|SRC EPROM Example
 
File:EPROM_Example.pdf|SRC EPROM Example
−
File:EPROM Example.sch|ExpressPCB
+
File:EPROM Example.sch|ExpressPCB EPROM Schematic
 
File:SRAM Example.pdf|SRC SRAM Example
 
File:SRAM Example.pdf|SRC SRAM Example
−
File:DRAM Example.pdf|SRC DRAM Example
+
File:SRAM Example.sch|ExpressPCB SRAM Schematic
−
File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh
+
File:DRAM_Example_Datapath.pdf|DRAM Example Datapath
 +
File:DRAM_Moore_Example.pdf|SRC DRAM (Moore FSM) Example
 +
File:DRAM_Moore_Refresh_Example.pdf|SRC DRAM Example W/Refresh (Moore FSM)
 +
File:DRAM Example.pdf|SRC DRAM (Mealy FSM) Example
 +
File:DRAM Example Refresh.pdf|SRC DRAM Example W/Refresh (Mealy FSM)
 +
File:DRAM_TYPES.pdf|DRAM Types
 
File:Cache Example.pdf|SRC Cache Example
 
File:Cache Example.pdf|SRC Cache Example
 +
File:SRC_Cache_Datapath.pdf|SRC Cache Datapath
 +
File:VIRTUAL_MEMORY.pdf|Virtual Memory Concepts
 +
File:MC68851.pdf|Motorola MC68851 MMU
 
</gallery>
 
</gallery>
 +
 +
[http://www.edn.com/design/systems-design/4399725/Memory-Hierarchy-Design---Part-6--The-Intel-Core-i7 Hennessy and Patterson on the Intel i7]
 +
 
[http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html Intel i7 Cache Article]
 
[http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html Intel i7 Cache Article]
  
Line 121: Line 189:
 
File:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|THREE-SLOT MULTI-MASTER SRC MOTHERBOARD
 
File:THREE-SLOT_MULTI-MASTER_SRC_MOTHERBOARD.pdf|THREE-SLOT MULTI-MASTER SRC MOTHERBOARD
 
File:PCI Lecture.pdf|PCI
 
File:PCI Lecture.pdf|PCI
−
File:X86_Chipset_Evolution.pdf‎|Intel PCI Chipset Evolution
+
File:X86_Chipset_Evolution.pdf|Intel PCI Chipset Evolution
−
File:Reflection Lecture.pdf|Parallel vs. Serial Buses
+
File:Reflection Lecture.pdf|Reflection Lecture (Parallel vs. Serial Buses)
 +
File:LTSPICE_TUTORIAL.pdf|LTSPICE IV Quick Tutorial
 
File:Reflection_Example.pdf|Reflection Example
 
File:Reflection_Example.pdf|Reflection Example
 
File:PCIe Lecture.pdf|PCIe
 
File:PCIe Lecture.pdf|PCIe
 
File:Coding Theory 001.pdf|Coding Theory 001
 
File:Coding Theory 001.pdf|Coding Theory 001
 
File:Hamming Code Example With Odd Parity.pdf|Hamming Codes
 
File:Hamming Code Example With Odd Parity.pdf|Hamming Codes
−
File:State Equal Output Moore Example.pdf|State Equal Output Moore Example
+
File:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example
 +
File:Ibm5160techref.pdf|IBM 5160 Technical Reference
 
</gallery>
 
</gallery>
−
[http://www.retroarchive.org/dos/docs/ibm5160techref.pdf IBM 5160 Technical Reference]
 
  
 
<gallery caption="Chapter 9">
 
<gallery caption="Chapter 9">
 
File:Ch9CSDA.pdf|Chapter 9
 
File:Ch9CSDA.pdf|Chapter 9
 +
File:640_MB_SUN_MICROSYSTEMS_DISK_1.JPG
 +
File:640_MB_SUN_MICROSYSTEMS_DISK_2.JPG
 
File:NTSC Video.pdf|NTSC Video
 
File:NTSC Video.pdf|NTSC Video
 
File:Video Example.pdf|Video Example
 
File:Video Example.pdf|Video Example
 
File:NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf|NVIDIA FERMI
 
File:NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf|NVIDIA FERMI
 
File:Basic_principles.pdf|Video Chapter
 
File:Basic_principles.pdf|Video Chapter
 +
File:2-Bit_Flash_ADC.pdf|2-Bit Pipelined Flash ADC
 +
File:R2R_DAC.pdf|R2R Digital-to-Analog Converter (DAC)
 
</gallery>
 
</gallery>
  
Line 145: Line 218:
 
File:DS92LV16.pdf|National DS92LV16 SERDES
 
File:DS92LV16.pdf|National DS92LV16 SERDES
 
File:usb_20.pdf|USB 2.0
 
File:usb_20.pdf|USB 2.0
 +
File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture
 +
</gallery>
 +
 +
<gallery caption="VHDL Tutorial">
 
File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture
 
File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture
 
</gallery>
 
</gallery>

Latest revision as of 16:46, 28 November 2017

  • Introduction

  • Introduction

  • Errata

  • Appendix A

  • Appendix C

  • SRC Reference

  • Chapter 1

  • Chapter 1

  • Chapter 2

  • Chapter 2

  • SRC RTN

  • Chapter 3

  • Chapter 3

  • Chapter 4

  • Chapter 4

  • Displacement-Based Addressing

  • One-Bus SRC Block Diagrams

  • One-Bus SRC RTN

  • One-Bus SRC VHDL

  • SRC VHDL Tutorial

  • Boole's Expansion Theorem

  • Xilinx Virtex 6 Configurable Logic Block User Guide

  • SRC User Constraint File

  • SRC Synthesis Report

  • SRC Place-and-Route Report

  • SRC Pinout Report

  • SRC Timing (Trace) Report

  • SRC Datasheet

  • One-Bus SRC with DCM VHDL

  • SRC with DCM Datasheet

  • One-Mux SRC Block Diagrams

  • Two-Bus SRC

  • Three-Bus SRC

  • Standard Cell SRC?

  • Chapter 5

  • Chapter 5

  • Patterson/Ditzel ACM SIGARCH Computer Architecture News Article on RISC

  • Table 5.1

  • Corrected Figure 5.15

  • Basic Pipelined SRC

  • Pipelined SRC

  • Pipelined SRC VHDL Source (Instructor Only)

  • Microprogrammed SRC Control Unit.pdf

    Microprogrammed SRC

  • Microprogrammed SRC Control

  • Microprogrammed SRC Control Store

  • Microcodedsrcvhdl.zip

    One-Bus Microcoded SRC VHDL

  • Microsoft Windows (TM) Version History

  • Microsoft Windows for Workgroups(TM) Version History

  • AMD K7 Presentation

  • AMD Hammer Presentation

  • VLIW Notes

  • Fisher Paper 1

  • Fisher Paper 2

  • Intel Itanium

  • Intel Itanium Software Developer's Guide

  • Transmeta Crusoe White Paper

  • IEEE Spectrum Article on Transmeta

  • HP Transmeta Crusoe Laptop

  • Intel PII MESI System (Circa 1998)

  • Intel 440FX Pentium Pro Chipset

  • Intel Pentium II Datasheet

  • Intel 440LX Pentium II Chipset

  • Intel Core I7-980X Product Brief

  • Intel Core I7-980X Diemap

  • MSI Protocol

  • Illinois (MESI) Protocol

  • Hyper-Threaded SRC Concept

  • SPARC T5

  • SPARC M6

  • Intel Xeon Phi Whitepaper

  • Intel Xeon Phi

  • Expressing Parallelism

  • Where to Go From Here

  • CPU History

Intel P4 Netburst CPU

Microcode

The Intel 8086/8088: The Original IBM PC CPU

The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286

The First 32-bit X86 CPU: The Intel 80386

The First Tightly Pipelined X86 CPU: The Intel 80486

Superscalar CPU History

The First Superscalar X86 CPU: The Intel P5

The First 64-bit X86 CPU: The AMD Opteron

Original AMD Athlon on Wikipedia

VLIW on Wikipedia

The Father of VLIW: Josh Fisher

Multiflow

VLIW at IBM

VLIW Tree-Instruction Example

Intel's First VLIW CPU (Failure): The i860

Itanium

How the Itanium Killed the Computer Industry

HP and Intel Effectively Kill off Itanium

HP TC 1000 Crusoe-Based Tablet PC

SMP on Wikipedia

Cache Coherence on Wikipedia

Mark Papmarcos on Linkedin

Thread (Computing) on Wikipedia

Simultaneous Multithreading on Wikipedia

Hyper-Threading on Wikipedia

SPARC T1 "Multi-threaded" CPU on Wikipedia

SPARC T3 "Multi-threaded" CPU on Wikipedia

Implementing Scalable Atomic Locks for Multi-Core Intel® EM64T and IA32 Architectures

History of Supercomputing on Wikipedia

Cluster Computing on Wikipedia

Intel Xeon Phi

  • Chapter 6

  • Chapter 6

  • Supplement 1

  • Supplement 2

  • Supplement 3

  • Chapter 7

  • Chapter 7

  • SRC EPROM Example

  • ExpressPCB EPROM Schematic

  • SRC SRAM Example

  • ExpressPCB SRAM Schematic

  • DRAM Example Datapath

  • SRC DRAM (Moore FSM) Example

  • SRC DRAM Example W/Refresh (Moore FSM)

  • SRC DRAM (Mealy FSM) Example

  • SRC DRAM Example W/Refresh (Mealy FSM)

  • DRAM Types

  • SRC Cache Example

  • SRC Cache Datapath

  • Virtual Memory Concepts

  • Motorola MC68851 MMU

Hennessy and Patterson on the Intel i7

Intel i7 Cache Article

  • Chapter 8

  • Chapter 8

  • Stereo Card Example

  • Stereo Card VHDL

  • IN & OUT RTN

  • Metastability Lecture

  • Metastability 1

  • Metastability 2

  • Multimastersrcvhdl.zip

    Multi-Master SRC VHDL

  • Bus-Master Stereo SRC Audio Card VHDL

  • THREE-SLOT MULTI-MASTER SRC MOTHERBOARD

  • PCI

  • Intel PCI Chipset Evolution

  • Reflection Lecture (Parallel vs. Serial Buses)

  • LTSPICE IV Quick Tutorial

  • Reflection Example

  • PCIe

  • Coding Theory 001

  • Hamming Codes

  • State Equal Output Moore Example

  • IBM 5160 Technical Reference

  • Chapter 9

  • Chapter 9

  • 640 MB SUN MICROSYSTEMS DISK 1.JPG
  • 640 MB SUN MICROSYSTEMS DISK 2.JPG

  • NTSC Video

  • Video Example

  • NVIDIA FERMI

  • Video Chapter

  • 2-Bit Pipelined Flash ADC

  • R2R Digital-to-Analog Converter (DAC)

  • Chapter 10

  • Chapter 10

  • RS232 Examples

  • MAX232 IC

  • National DS92LV16 SERDES

  • USB 2.0

  • VHDL Lecture

  • VHDL Tutorial

  • VHDL Lecture

Retrieved from "http://classes.engineering.wustl.edu/cse362/index.php?title=Lecture_Notes&oldid=1678"