Difference between revisions of "Lecture Notes"
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File:Pipelined SRC.pdf|Pipelined SRC | File:Pipelined SRC.pdf|Pipelined SRC | ||
File:src.pdf|Pipelined SRC VHDL Source (Instructor Only) | File:src.pdf|Pipelined SRC VHDL Source (Instructor Only) | ||
| − | File: | + | File:Microprogrammed SRC Control Unit.pdf|Microprogrammed SRC |
| + | File:Control.pdf|Microprogrammed SRC Control | ||
| + | File:Controlstore.pdf|Microprogrammed SRC Control Store | ||
| + | File:Microcodedsrcvhdl.zip|One-Bus Microcoded SRC VHDL | ||
File:k7pres.pdf|AMD K7 Presentation | File:k7pres.pdf|AMD K7 Presentation | ||
File:MPF_Hammer_Presentation.pdf|AMD Hammer Presentation | File:MPF_Hammer_Presentation.pdf|AMD Hammer Presentation | ||
| + | File:VLIW.pdf|VLIW Notes | ||
| + | File:Itanium.ua_ovw.pdf|Intel Itanium | ||
File:paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper | File:paper_aklaiber_19jan00.pdf|Transmeta Crusoe White Paper | ||
File:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop | File:Transmeta_Laptop.pdf|HP Transmeta Crusoe Laptop | ||
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File:Intel_Core_i7-980X_Product_Brief.pdf|Intel Core I7-980X Product Brief | File:Intel_Core_i7-980X_Product_Brief.pdf|Intel Core I7-980X Product Brief | ||
File:I7-980X_Diemap.jpg|Intel Core I7-980X Diemap | File:I7-980X_Diemap.jpg|Intel Core I7-980X Diemap | ||
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File:Expressing_Parallelism.pdf| Expressing Parallelism | File:Expressing_Parallelism.pdf| Expressing Parallelism | ||
File:Where_To_Go_From_Here.pdf| Where to Go From Here | File:Where_To_Go_From_Here.pdf| Where to Go From Here | ||
Revision as of 16:24, 19 November 2013
- Introduction
Introduction
Errata
Appendix A
Appendix C
SRC Reference
- Chapter 1
Chapter 1
- Chapter 2
Chapter 2
SRC RTN
- Chapter 3
Chapter 3
- Chapter 4
Chapter 4
One-Bus SRC Block Diagrams
One-Bus SRC RTN
One-Bus SRC VHDL
SRC VHDL Tutorial
Xilinx Virtex 6 Configurable Logic Block User Guide
SRC Synthesis Report
SRC Place-and-Route Report
SRC Timing (Trace) Report
One-Mux SRC Block Diagrams
Two-Bus SRC
Three-Bus SRC
Standard Cell SRC?
- Chapter 5
Chapter 5
Table 5.1
Corrected Figure 5.15
Pipelined SRC
Pipelined SRC VHDL Source (Instructor Only)
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
Microprogrammed SRC Control
Microprogrammed SRC Control Store
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
AMD K7 Presentation
AMD Hammer Presentation
VLIW Notes
Intel Itanium
Transmeta Crusoe White Paper
HP Transmeta Crusoe Laptop
Intel Core I7-980X Product Brief
Intel Core I7-980X Diemap
Expressing Parallelism
Where to Go From Here
CPU History
The First Superscalar X86 CPU: The P5
Original AMD Athlon on Wikipedia
HP TC 1000 Crusoe-Based Tablet PC
- Chapter 6
Chapter 6
Supplement 1
Supplement 2
Supplement 3
- Chapter 7
Chapter 7
SRC EPROM Example
ExpressPCB
SRC SRAM Example
SRC DRAM Example
SRC DRAM Example W/Refresh
SRC Cache Example
- Chapter 8
Chapter 8
Stereo Card Example
Stereo Card VHDL
IN & OUT RTN
Metastability Lecture
Metastability 1
Metastability 2
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
Bus-Master Stereo SRC Audio Card VHDL
THREE-SLOT MULTI-MASTER SRC MOTHERBOARD
PCI
Intel PCI Chipset Evolution
Parallel vs. Serial Buses
Reflection Example
PCIe
Coding Theory 001
Hamming Codes
- State Equal Output Moore Example.pdf
State Equal Output Moore Example
- Chapter 9
Chapter 9
NTSC Video
Video Example
NVIDIA FERMI
Video Chapter
- Chapter 10
Chapter 10
RS232 Examples
MAX232 IC
National DS92LV16 SERDES
USB 2.0
VHDL Lecture
