Difference between revisions of "Lecture Notes"
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File:Table_5P1.pdf|Table 5.1 | File:Table_5P1.pdf|Table 5.1 | ||
File:Pipelined SRC.pdf|Pipelined SRC | File:Pipelined SRC.pdf|Pipelined SRC | ||
+ | File:src.pdf|Pipelined SRC VHDL Source (Instructor Only) | ||
File:VLIW.pdf|VLIW Notes | File:VLIW.pdf|VLIW Notes | ||
File:k7pres.pdf|AMD K7 Presentation | File:k7pres.pdf|AMD K7 Presentation |
Revision as of 15:24, 17 November 2011
- Testbench.pdf
One-Bus SRC Simulation
- Synthesis Report.pdf
XC3S500E-4 SRC Synthesis Report
- Place&Route.pdf
XC3S500E-4 SRC Place and Route Report
- Timing Report.pdf
XC3S500E-4 SRC Timing Report
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
The First Superscalar X86 CPU: The P5
Original AMD Athlon on Wikipedia
HP TC 1000 Crusoe-Based Tablet PC
- Eprom Example.pdf
SRC EPROM Example
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
- State Equal Output Moore Example.pdf
State Equal Output Moore Example