Difference between revisions of "Syllabus"
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## Hardware Implications of RTN | ## Hardware Implications of RTN | ||
# Processor Design | # Processor Design | ||
− | ## Design Process | + | ## Introduction to the Design Process |
− | ## | + | ## 1-Bus SRC Microarchitecture (w/VHDL Model)* |
− | ## Data | + | ### Data Path |
− | ## | + | ### Control |
− | ## | + | ## 2-Bus SRC Microarchitecture |
− | ## | + | ## 3-Bus SRC Microarchitecture |
− | ## Reset | + | ## Reset Considerations |
− | ## | + | ## Exceptions/Interrupts |
# Memory System Design | # Memory System Design | ||
## Components of the Memory System | ## Components of the Memory System |
Revision as of 18:47, 25 April 2011
- The General Purpose Machine
- User's View
- Programmer's View
- Architect's View
- Logic Designer's View
- Machines, Machine Languages and Digital Logic
- Classification of Computers
- Instruction Sets
- Introduction of the SRC (Simple RISC Computer)
- Using RTN (Register Transfer Notation)
- Addressing Modes
- Hardware Implications of RTN
- Processor Design
- Introduction to the Design Process
- 1-Bus SRC Microarchitecture (w/VHDL Model)*
- Data Path
- Control
- 2-Bus SRC Microarchitecture
- 3-Bus SRC Microarchitecture
- Reset Considerations
- Exceptions/Interrupts
- Memory System Design
- Components of the Memory System
- Memory Types
- EPROM
- Example: SRC EPROM Memory Subsystem*
- SRAM
- Example: SRC SRAM Memory Subsystem*
- DRAM (FPM, EDO, VRAM)
- Example: SRC DRAM Memory Subsystem*
- SDRAM (SDRAM, DDR, DDR2)
- FLASH Memory
- EPROM
- Memory Modules
- Example: 72-pin 16 MB FPM DRAM DIMM
- Example: 144-pin 64 MB EDO DRAM DIMM
- Example: 184-pin 128 MB ECC DDR DRAM DIMM
- Two-Level Hierarchy
- Cache
- Associative Caches*
- Direct-Mapped Caches*
- N-Way Set-Associative Caches*
- Read/Write/Replacement Policies*
- Virtual Memory
- Segmentation
- Paging
- Regaining Lost Ground: The TLB
- Overall Memory Subsystem with Introduction to I/O Issues
- Input/Output
- I/O Subsystems Overview
- Programmed I/O
- General Principles
- Example: Programmed I/O on the SRC (w/VHDL Model)*
- Interrupt-Driven I/O
- DMA (Direct Memory Access)
- General Principles
- Example: DMA Engine for the SRC (w/VHDL Model)*
- Example: PCI(e)
- Parallel vs. Serial I/O Buses
- I/O Error Detection and Correction*
- Parity
- Hamming/SECDED Codes (ECC Memory)
- CRC Codes
- Advanced Topics
- Pipelining
- General Principles
- Example: Pipelined SRC (w/VHDL Model)*
- Instruction Level Parallelism
- Superscalar Processors
- General Principles
- Example: Intel Pentium (1st Superscalar X86 CPU)
- Example: AMD K7 (9-issue, Speculative Out-of-Order Execution, etc.)
- VLIW Machines
- General Principles
- Example: IBM VLIW Prototype
- Example: Intel Itanium/EPIC
- Superscalar Processors
- Microprogramming
- General Principles
- Example: Microprogrammed SRC (w/VHDL Model)*
- Code Morphing
- Example: Transmeta Crusoe
- Extending the Address Space
- 16- to 32-bit: Intel 80386
- 32- to 64-bit: AMD Hammer vs Intel Itanium
- Multicore CPUs
- Example: Intel i7-980X
- Pipelining