Syllabus

1. The General Purpose Machine
   1. User's View
   2. Programmer's View
   3. Architect's View
   4. Logic Designer's View
2. Machines, Machine Languages and Digital Logic
   1. Classification of Computers
   2. Instruction Sets
   3. Introduction of the SRC (Simple RISC Computer)
   4. Using RTN (Register Transfer Notation)
   5. Addressing Modes
   6. Hardware Implications of RTN
3. Processor Design
   1. Design Process
   2. SRC 1-Bus Microarchitecture
   3. Data Paths
   4. Logic Design
   5. Control
   6. Multiple-Bus Designs
   7. Reset
   8. Design Expectations
4. Memory System Design
   1. Components of the Memory System
   2. RAM Structure
   3. Memory Modules
   4. Two-Level Hierarchy
   5. Cache
   6. Virtual Memory
   7. Memory Subsystem in the Computer
5. Input/Output
   1. I/O Subsystems Overview
   2. Programmed I/O
      1. General Principles
      2. Example: Programmed I/O on the SRC*
   3. Interrupt-Driven I/O
   4. DMA (Direct Memory Access)
      1. General Principles
      2. Example: DMA Engine for the SRC (w/VHDL Model)*
      3. Example: PCI(e)
         1. Parallel vs. Serial I/O Buses
   5. I/O Data Format Change
   6. Error Control
6. Advanced Topics
   1. Pipelining
      1. General Principles
      2. Example: Pipelined SRC (w/VHDL Model)*
   2. Instruction Level Parallelism
      1. Superscalar Processors
         1. General Principles
         2. Example: Intel Pentium (1st Superscalar X86 CPU)
         3. Example: AMD K7 (9-issue, Speculative Out-of-Order Execution, etc.)
      2. VLIW Machines
         1. General Principles
         2. Example: IBM VLIW Prototype
         3. Example: Intel Itanium/EPIC
   3. Microprogramming
      1. General Principles
      2. Example: Microprogrammed SRC (w/VHDL Model)*
   4. Code Morphing
      1. Example: Transmeta Crusoe
   5. Extending the Address Space
      1. 16- to 32-bit: Intel 80386
      2. 32- to 64-bit: AMD Hammer vs Intel Itanium
   6. Multicore CPUs
      1. Example: Intel i7-980X