Difference between revisions of "Syllabus"
From CSE362 Wiki
Jump to navigationJump to searchLine 41: | Line 41: | ||
## Instruction Level Parallelism | ## Instruction Level Parallelism | ||
### Superscalar Processors | ### Superscalar Processors | ||
+ | #### General Principles | ||
+ | #### AMD K7 | ||
### VLIW Machines | ### VLIW Machines | ||
#### General Principles | #### General Principles |
Revision as of 15:53, 25 April 2011
- The General Purpose Machine
- User's View
- Programmer's View
- Architect's View
- Logic Designer's View
- Machines, Machine Languages and Digital Logic
- Classification of Computers
- Instruction Sets
- Introduction of the SRC (Simple RISC Computer)
- Using RTN (Register Transfer Notation)
- Addressing Modes
- Hardware Implications of RTN
- Processor Design
- Design Process
- SRC 1-Bus Microarchitecture
- Data Paths
- Logic Design
- Control
- Multiple-Bus Designs
- Reset
- Design Expectations
- Memory System Design
- Components of the Memory System
- RAM Structure
- Memory Modules
- Two-Level Hierarchy
- Cache
- Virtual Memory
- Memory Subsystem in the Computer
- Input/Output
- I/O Subsystems
- Programmed I/O
- Interrupts
- DMA (Direct Memory Access)
- I/O Data Format Change
- Error Control
- Advanced Topics
- Pipelining
- General Principles
- Pipelined SRC (w/VHDL Model)
- Instruction Level Parallelism
- Superscalar Processors
- General Principles
- AMD K7
- VLIW Machines
- General Principles
- IBM VLIW Prototype
- Superscalar Processors
- Microprogramming
- Code Morphing
- Transmeta Crusoe
- Pipelining