Difference between revisions of "Syllabus"
From CSE362 Wiki
Jump to navigationJump to searchLine 37: | Line 37: | ||
# Advanced Topics | # Advanced Topics | ||
## Pipelining | ## Pipelining | ||
− | ## Instruction Parallelism | + | ## Instruction Level Parallelism |
+ | ### Superscalar Processors | ||
+ | ### VLIW Machines | ||
## Microprogramming | ## Microprogramming | ||
## Transmeta Crusoe | ## Transmeta Crusoe |
Revision as of 15:45, 25 April 2011
- The General Purpose Machine
- User's View
- Programmer's View
- Architect's View
- Logic Designer's View
- Machines, Machine Languages and Digital Logic
- Classification of Computers
- Instruction Sets
- Introduction of the SRC (Simple RISC Computer)
- Using RTN (Register Transfer Notation)
- Addressing Modes
- Hardware Implications of RTN
- Processor Design
- Design Process
- SRC 1-Bus Microarchitecture
- Data Paths
- Logic Design
- Control
- Multiple-Bus Designs
- Reset
- Design Expectations
- Memory System Design
- Components of the Memory System
- RAM Structure
- Memory Modules
- Two-Level Hierarchy
- Cache
- Virtual Memory
- Memory Subsystem in the Computer
- Input/Output
- I/O Subsystems
- Programmed I/O
- Interrupts
- DMA (Direct Memory Access)
- I/O Data Format Change
- Error Control
- Advanced Topics
- Pipelining
- Instruction Level Parallelism
- Superscalar Processors
- VLIW Machines
- Microprogramming
- Transmeta Crusoe