Difference between revisions of "Lecture Notes"
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File:Microcodedsrcvhdl.zip|One-Bus Microcoded SRC VHDL | File:Microcodedsrcvhdl.zip|One-Bus Microcoded SRC VHDL | ||
</gallery> | </gallery> | ||
− | [http://en.wikipedia.org/wiki/P5_ | + | [http://en.wikipedia.org/wiki/P5_(microarchitecture)/The First Superscalar X86 CPU: The P5] |
[http://www.research.ibm.com/vliw/ VLIW at IBM] | [http://www.research.ibm.com/vliw/ VLIW at IBM] |
Revision as of 15:30, 30 November 2010
- Testbench.pdf
One-Bus SRC Simulation
- Synthesis Report.pdf
XC3S500E-4 SRC Synthesis Report
- Place&Route.pdf
XC3S500E-4 SRC Place and Route Report
- Timing Report.pdf
XC3S500E-4 SRC Timing Report
- Microprogrammed SRC Control Unit.pdf
Microprogrammed SRC
- Microcodedsrcvhdl.zip
One-Bus Microcoded SRC VHDL
First Superscalar X86 CPU: The P5
Original AMD Athlon on Wikipedia
- Eprom Example.pdf
SRC EPROM Example
- Multimastersrcvhdl.zip
Multi-Master SRC VHDL
- State Equal Output Moore Example.pdf
State Equal Output Moore Example