Difference between revisions of "Lecture Notes"

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<gallery caption="Chapter 5">
 
<gallery caption="Chapter 5">
 
File:Ch5CSDA.pdf|Chapter 5
 
File:Ch5CSDA.pdf|Chapter 5
 +
File:RISC.pdf|Patterson/Ditzel ACM SIGARCH Computer Architecture News Article on RISC
 
File:Table_5P1.pdf|Table 5.1
 
File:Table_5P1.pdf|Table 5.1
 
File:Corrected_Figure_5.15.pdf|Corrected Figure 5.15
 
File:Corrected_Figure_5.15.pdf|Corrected Figure 5.15
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File:Hyperthreaded_SRC_Concept.pdf|Hyper-Threaded SRC Concept
 
File:Hyperthreaded_SRC_Concept.pdf|Hyper-Threaded SRC Concept
 
File:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5
 
File:O13-024-sparc-t5-architecture-1920540.pdf|SPARC T5
 +
File:Sparc-m6-processor-ds-2015586.pdf|SPARC M6
 
File:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi Whitepaper
 
File:Intel_Xeon_Phi_Whitepaper.pdf|Intel Xeon Phi Whitepaper
 
File:High-performance-xeon-phi-coprocessor-brief.pdf|Intel Xeon Phi
 
File:High-performance-xeon-phi-coprocessor-brief.pdf|Intel Xeon Phi
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File:NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf|NVIDIA FERMI
 
File:NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf|NVIDIA FERMI
 
File:Basic_principles.pdf|Video Chapter
 
File:Basic_principles.pdf|Video Chapter
File:2-Bit_Flash_ADC.png|2-Bit Pipelined Flash ADC
+
File:2-Bit_Flash_ADC.pdf|2-Bit Pipelined Flash ADC
 +
File:R2R_DAC.pdf|R2R Digital-to-Analog Converter (DAC)
 
</gallery>
 
</gallery>
  

Latest revision as of 16:46, 28 November 2017

Intel P4 Netburst CPU

Microcode

The Intel 8086/8088: The Original IBM PC CPU

The First 16-bit X86 CPU with Memory Management and Protected Mode: The Intel 80286

The First 32-bit X86 CPU: The Intel 80386

The First Tightly Pipelined X86 CPU: The Intel 80486

Superscalar CPU History

The First Superscalar X86 CPU: The Intel P5

The First 64-bit X86 CPU: The AMD Opteron

Original AMD Athlon on Wikipedia

VLIW on Wikipedia

The Father of VLIW: Josh Fisher

Multiflow

VLIW at IBM

VLIW Tree-Instruction Example

Intel's First VLIW CPU (Failure): The i860

Itanium

How the Itanium Killed the Computer Industry

HP and Intel Effectively Kill off Itanium

HP TC 1000 Crusoe-Based Tablet PC

SMP on Wikipedia

Cache Coherence on Wikipedia

Mark Papmarcos on Linkedin

Thread (Computing) on Wikipedia

Simultaneous Multithreading on Wikipedia

Hyper-Threading on Wikipedia

SPARC T1 "Multi-threaded" CPU on Wikipedia

SPARC T3 "Multi-threaded" CPU on Wikipedia

Implementing Scalable Atomic Locks for Multi-Core Intel® EM64T and IA32 Architectures

History of Supercomputing on Wikipedia

Cluster Computing on Wikipedia

Intel Xeon Phi

Hennessy and Patterson on the Intel i7

Intel i7 Cache Article