Difference between revisions of "Syllabus"
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− | + | # The General Purpose Machine | |
+ | ## User's View | ||
+ | ## Programmer's View | ||
+ | ## Architect's View | ||
+ | ## Logic Designer's View | ||
+ | # Machines, Machine Languages and Digital Logic | ||
+ | ## Classification of Computers | ||
+ | ### 4-, 3-, 2-, 1-, and 0-Address Instructions | ||
+ | ### Stack-based Machines | ||
+ | ### General Register Machines (1 1/2 Address Machines) | ||
+ | ### Load/Store Machines | ||
+ | ## Instruction Types | ||
+ | ### Data Movement Instructions | ||
+ | ### Arithmetic and Logic Instructions | ||
+ | ### Branch Instructions | ||
+ | ## Introduction of the SRC (Simple RISC Computer) | ||
+ | ### SRC Instruction Set | ||
+ | ### SRC Assembler/Simulator* | ||
+ | ## Using RTN (Register Transfer Notation) | ||
+ | ### RTN Description of the SRC* | ||
+ | ## Addressing Modes (w/RTN Descriptions) | ||
+ | ### Immediate Addressing | ||
+ | ### Direct Addressing | ||
+ | ### Indirect Addressing | ||
+ | ### Register Direct Addressing | ||
+ | ### Register Indirect Addressing | ||
+ | ### Displacement-based Addressing | ||
+ | ### Indexed Addressing | ||
+ | ### Relative Addressing | ||
+ | ## Hardware Implications of RTN | ||
+ | # Processor Design | ||
+ | ## Introduction to the Design Process | ||
+ | ## 1-Bus SRC Microarchitecture (w/VHDL Model)* | ||
+ | ### Data Path | ||
+ | ### Control | ||
+ | ## 2-Bus SRC Microarchitecture | ||
+ | ## 3-Bus SRC Microarchitecture | ||
+ | ## Reset Considerations | ||
+ | ## Exceptions/Interrupts | ||
+ | # Memory System Design | ||
+ | ## Components of the Memory System | ||
+ | ## Memory Types | ||
+ | ### EPROM | ||
+ | #### Example: SRC EPROM Memory Subsystem* | ||
+ | ### SRAM | ||
+ | #### Example: SRC SRAM Memory Subsystem* | ||
+ | ### DRAM (FPM, EDO, VRAM) | ||
+ | #### Example: SRC DRAM Memory Subsystem* | ||
+ | ### SDRAM (SDRAM, DDR, DDR2) | ||
+ | ### FLASH Memory | ||
+ | ## Memory Modules | ||
+ | ### Example: 72-pin 16 MB FPM DRAM DIMM | ||
+ | ### Example: 144-pin 64 MB EDO DRAM DIMM | ||
+ | ### Example: 184-pin 128 MB ECC DDR DRAM DIMM | ||
+ | ## Two-Level Hierarchy | ||
+ | ## Cache | ||
+ | ### Associative Caches* | ||
+ | ### Direct-Mapped Caches* | ||
+ | ### N-Way Set-Associative Caches* | ||
+ | ### Read/Write/Replacement Policies* | ||
+ | ## Virtual Memory | ||
+ | ### Segmentation | ||
+ | ### Paging | ||
+ | ### Regaining Lost Ground: The TLB | ||
+ | ## Overall Memory Subsystem with Introduction to I/O Issues | ||
+ | # Input/Output | ||
+ | ## I/O Subsystems Overview | ||
+ | ## Programmed I/O | ||
+ | ### General Principles | ||
+ | ### Example: SRC Stereo Audio Card Using Programmed I/O(w/VHDL Model)* | ||
+ | ## Interrupt-Driven I/O | ||
+ | ## DMA (Direct Memory Access) | ||
+ | ### General Principles | ||
+ | ### Example: SRC Stereo Audio Card Using DMA Engine(w/VHDL Model)* | ||
+ | ### Example: PCI(e) | ||
+ | #### Parallel vs. Serial I/O Buses | ||
+ | ## I/O Error Detection and Correction* | ||
+ | ### Parity | ||
+ | ### Hamming/SECDED Codes (ECC Memory) | ||
+ | ### CRC Codes | ||
+ | # Peripherals and Peripheral Buses | ||
+ | ## RS-232C | ||
+ | ## Universal Serial Bus V2.0 | ||
+ | ## IEEE 1394 (Firewire) | ||
+ | ## Video | ||
+ | ### RS-170 | ||
+ | ### NTSC | ||
+ | ### VGA, SVGA, HDTV | ||
+ | ### GPUs | ||
+ | #### Example: NVIDIA FERMI CUDA GPU Architecture | ||
+ | #### Example: Simple GPU for the 1-bus SRC | ||
+ | ## Hard Disks | ||
+ | # Advanced Topics | ||
+ | ## Pipelining | ||
+ | ### General Principles | ||
+ | ### Example: Pipelined SRC (w/VHDL Model)* | ||
+ | ### Flynn Limit | ||
+ | ## Instruction Level Parallelism | ||
+ | ### Superscalar Processors | ||
+ | #### General Principles | ||
+ | #### Example: Intel Pentium (1st Superscalar X86 CPU) | ||
+ | #### Example: AMD K7 (9-issue, Speculative Out-of-Order Execution, etc.) | ||
+ | ### VLIW Machines | ||
+ | #### General Principles | ||
+ | #### Example: IBM VLIW Prototype | ||
+ | #### Example: Intel Itanium/EPIC | ||
+ | ## Microprogramming | ||
+ | ### General Principles | ||
+ | ### Example: Microprogrammed SRC (w/VHDL Model)* | ||
+ | ## Code Morphing | ||
+ | ### Example: Transmeta Crusoe | ||
+ | ## Extending the Address Space | ||
+ | ### 16- to 32-bit: Intel 80386 | ||
+ | ### 32- to 64-bit: AMD Hammer vs Intel Itanium | ||
+ | ## Multicore CPUs | ||
+ | ### Amdahl's Law | ||
+ | ### Symetric Multiprocessing (SMP) | ||
+ | #### Example: Intel i7-980X | ||
+ | ### Cache Coherency | ||
+ | ####MESI (Illinois Protocol) | ||
+ | ####MESIF (Intel starting with Nahelem) | ||
+ | ####MOESI (AMD starting with AMD64) | ||
+ | ### Simultaneous Multi-Threading (SMT) | ||
+ | #### Intel Hyperthreading | ||
+ | #### Sun Microsystems Barrel Processors | ||
+ | ### OpenMP |
Revision as of 16:23, 17 July 2015
- The General Purpose Machine
- User's View
- Programmer's View
- Architect's View
- Logic Designer's View
- Machines, Machine Languages and Digital Logic
- Classification of Computers
- 4-, 3-, 2-, 1-, and 0-Address Instructions
- Stack-based Machines
- General Register Machines (1 1/2 Address Machines)
- Load/Store Machines
- Instruction Types
- Data Movement Instructions
- Arithmetic and Logic Instructions
- Branch Instructions
- Introduction of the SRC (Simple RISC Computer)
- SRC Instruction Set
- SRC Assembler/Simulator*
- Using RTN (Register Transfer Notation)
- RTN Description of the SRC*
- Addressing Modes (w/RTN Descriptions)
- Immediate Addressing
- Direct Addressing
- Indirect Addressing
- Register Direct Addressing
- Register Indirect Addressing
- Displacement-based Addressing
- Indexed Addressing
- Relative Addressing
- Hardware Implications of RTN
- Classification of Computers
- Processor Design
- Introduction to the Design Process
- 1-Bus SRC Microarchitecture (w/VHDL Model)*
- Data Path
- Control
- 2-Bus SRC Microarchitecture
- 3-Bus SRC Microarchitecture
- Reset Considerations
- Exceptions/Interrupts
- Memory System Design
- Components of the Memory System
- Memory Types
- EPROM
- Example: SRC EPROM Memory Subsystem*
- SRAM
- Example: SRC SRAM Memory Subsystem*
- DRAM (FPM, EDO, VRAM)
- Example: SRC DRAM Memory Subsystem*
- SDRAM (SDRAM, DDR, DDR2)
- FLASH Memory
- EPROM
- Memory Modules
- Example: 72-pin 16 MB FPM DRAM DIMM
- Example: 144-pin 64 MB EDO DRAM DIMM
- Example: 184-pin 128 MB ECC DDR DRAM DIMM
- Two-Level Hierarchy
- Cache
- Associative Caches*
- Direct-Mapped Caches*
- N-Way Set-Associative Caches*
- Read/Write/Replacement Policies*
- Virtual Memory
- Segmentation
- Paging
- Regaining Lost Ground: The TLB
- Overall Memory Subsystem with Introduction to I/O Issues
- Input/Output
- I/O Subsystems Overview
- Programmed I/O
- General Principles
- Example: SRC Stereo Audio Card Using Programmed I/O(w/VHDL Model)*
- Interrupt-Driven I/O
- DMA (Direct Memory Access)
- General Principles
- Example: SRC Stereo Audio Card Using DMA Engine(w/VHDL Model)*
- Example: PCI(e)
- Parallel vs. Serial I/O Buses
- I/O Error Detection and Correction*
- Parity
- Hamming/SECDED Codes (ECC Memory)
- CRC Codes
- Peripherals and Peripheral Buses
- RS-232C
- Universal Serial Bus V2.0
- IEEE 1394 (Firewire)
- Video
- RS-170
- NTSC
- VGA, SVGA, HDTV
- GPUs
- Example: NVIDIA FERMI CUDA GPU Architecture
- Example: Simple GPU for the 1-bus SRC
- Hard Disks
- Advanced Topics
- Pipelining
- General Principles
- Example: Pipelined SRC (w/VHDL Model)*
- Flynn Limit
- Instruction Level Parallelism
- Superscalar Processors
- General Principles
- Example: Intel Pentium (1st Superscalar X86 CPU)
- Example: AMD K7 (9-issue, Speculative Out-of-Order Execution, etc.)
- VLIW Machines
- General Principles
- Example: IBM VLIW Prototype
- Example: Intel Itanium/EPIC
- Superscalar Processors
- Microprogramming
- General Principles
- Example: Microprogrammed SRC (w/VHDL Model)*
- Code Morphing
- Example: Transmeta Crusoe
- Extending the Address Space
- 16- to 32-bit: Intel 80386
- 32- to 64-bit: AMD Hammer vs Intel Itanium
- Multicore CPUs
- Amdahl's Law
- Symetric Multiprocessing (SMP)
- Example: Intel i7-980X
- Cache Coherency
- MESI (Illinois Protocol)
- MESIF (Intel starting with Nahelem)
- MOESI (AMD starting with AMD64)
- Simultaneous Multi-Threading (SMT)
- Intel Hyperthreading
- Sun Microsystems Barrel Processors
- OpenMP
- Pipelining