Lecture Notes

• Course Introduction
• Chapter 1
• Chapter 2
• Chapter 3
• -----Synthesizable VHDL (2016 Version)
• Vivado Simulation Tutorial 1
• Vivado Simulation Tutorial 2 (Forcing a Clock)
• Full Vivado Tutorial (John MacKay)
• Boole's Expansion Theorem
• Chapter 4
• First Counter
• Second Counter
• Oscillators and Clock Distribution
• Definitions and Theorems for Sequential Machines
• Minimizing Completely Specified Machines
• Chapter 5
• Chapter 6
• Chapter 7
• Chapter 8
• Chapter 9
• Chapter 10
• Chapter 11
• Chapter 12
• Anomalous Behavior of Synchronizer and Arbiter Circuits
• Measured Flip-Flop Responses to Marginal Triggering

Links:

Vivado Clock Constraints Tutorial

VGA Timing