Lecture Notes

• Course Roster

• Course Introduction
• Chapter 1
• -----The Reflected Binary (Gray) Code
• Chapter 2
• Chapter 3
• -----Synthesizable VHDL (2016 Version)
• -----Vivado Simulation Tutorial 1
• -----Vivado Simulation Tutorial 2 (Forcing a Clock)
• -----Full Vivado Tutorial (John MacKay)
• -----Boole's Expansion Theorem
• Chapter 4
• -----NOR SR Latch
• -----First Counter
• -----Second Counter
• -----Oscillators and Clock Distribution
• -----Definitions and Theorems for Sequential Machines
• -----Minimizing Completely Specified Machines
• Chapter 5
• Chapter 6

• The Really Simple RISC Computer (RSRC)
• ---Using Babbage's Difference Engine to Introduce Computer Architecture (instructor Only)
• ---RSRC CONTROL.VHD (Instructor Only)
• ---RSRC ALU.VHD (Instructor Only)
• ---RSRC EPROM.VHD (Instructor Only)
• ---RSRC SRAM.VHD (Instructor Only)
• ---RSRC.VHD (Instructor Only)
• ---RSRC TESTBENCH.VHD (Instructor Only)
• RSRC Abstract RTN
• 1Kx32 RSRC Memory Subsystem
• RSRC/SRC Displacement-Based Addressing
• SRC Documentation
• ---1-Bus SRC Block Diagram (From Heuring and Jordan)
• ---2-Bus SRC Block Diagram (From Heuring and Jordan)
• ---3-Bus SRC Block Diagram (From Heuring and Jordan)
• ------3-Bus SRC Register File (From Heuring and Jordan)

• Chapter 7
• Chapter 8
• Chapter 9
• Chapter 10
• Chapter 11
• Chapter 12
• Anomalous Behavior of Synchronizer and Arbiter Circuits
• Measured Flip-Flop Responses to Marginal Triggering

Links:

CSE 362M Chapter 7

SRC SIMULATOR

Vivado Clock Constraints Tutorial

VGA Timing