Difference between revisions of "Lecture Notes"
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[https://davidkessner.wordpress.com/2011/06/05/adc-in-an-fpga-part-2/ ADC in an FPGA (Part 2)] | [https://davidkessner.wordpress.com/2011/06/05/adc-in-an-fpga-part-2/ ADC in an FPGA (Part 2)] | ||
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| + | [http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_constraints_timing_strategies.htm Xilinx ISE Timing Constraints Strategies] | ||
[http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] | [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] | ||
Revision as of 20:18, 16 February 2015
- Course Introduction
- Use Advanced PCB Technology to Produce 50% Smaller Product Designs
- Reflection Lecture
- Maximum ExpressPCB Trace Impedance
- LVDS Fundamentals
- R-2R DAC Circuit
- R-2R DAC SPICE DECK
- R-2R DAC Simulation
- Understanding Flash ADCs
- Fermilab ADC/TDC in FPGA Paper
- Analog Ramp Generator
- Altera Delta-Sigma ADC in FPGA Paper
- Xilinx Modified Delta-Sigma ADC in FPGA Paper
- Lattice Semiconductor ADC White Paper
- Successive Approximation ADC in FPGA Paper
- Modified Delta-Sigma SPICE Model
- Example 8-bit 210 Msample/s Current Output DAC
- Example 14-bit 125 Msample/s Current Output DAC
- Example 16-bit 2.5 Gsample/s Current Output DAC
- Example 12-bit 4 Gs/s ADC
- Oscillators and Clock Distribution
- Lumped Lecture
- Spartan 6 FPGA Clocking Resources User Guide
- VHDL Lecture
- Xilinx ISE Simulation Tutorial
- State Equal Output Moore Machine Example
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
- IEEE Code of Ethics
- Employment Contract
Links:
PCB Trace Impedance Calculator]
