Syllabus

SYLLABUS

LECTURE	DATE	MATERIAL	PREPARATION	ASSIGNED	DUE
1	AUG 28	Course Introduction Number Systems Base Conversion Arithmetic Operations Codes	Course Introduction Chapter 1 The Reflected Binary (Gray) Code
2	AUG 30	Boolean Algebra The Consensus Theorem Introduction to K-Maps	Chapter 2
3	SEPT 6	Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder	Chapter 2 Chapter 3
4	SEPT 11	Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The Mux The Decoder Implementing Circuits Using Muxes	Chapter 2 Chapter 3
5	SEPT 13	Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass)	Standard Cell Circuit VHDL Tutorial Vivado Simulation Tutorial 1 Full Vivado Tutorial Boole's Expansion Theorem
6	SEPT 18	Boole's Expansion Theorem (Second Pass) FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX)	Chapter 5
7	SEPT 20	Digilent Development Board Concepts of VCCIO and Core Voltage Demo Board Schematic (LEDs, Switches)	Manual Schematics	Lab 1	Homework 3