Difference between revisions of "Syllabus"
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|SEPT 6 | |SEPT 6 | ||
|Standard Forms: POS Notation<br />Two-Level Circuit Optimization Using K-Maps<br />Proving Identities Using K-Maps<br />The XOR Gate<br />The Half Adder<br />The Full Adder<br />The Ripple-Carry Adder | |Standard Forms: POS Notation<br />Two-Level Circuit Optimization Using K-Maps<br />Proving Identities Using K-Maps<br />The XOR Gate<br />The Half Adder<br />The Full Adder<br />The Ripple-Carry Adder | ||
| − | |[[media:Mano_ch02_images.pdf|Chapter 2]] | + | |[[media:Mano_ch02_images.pdf|Chapter 2]]<br />[[media:Mano_ch03_images.pdf|Chapter 3]] |
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|SEPT 11 | |SEPT 11 | ||
|Essential Prime Implicants and Optimized Expressions<br />Standard Forms: SOP Notation<br />Five- and Six-Variable K-Maps<br />Don’t cares<br />Gate propagation delay<br />The Mux<br />The Decoder<br />Implementing Circuits Using Muxes | |Essential Prime Implicants and Optimized Expressions<br />Standard Forms: SOP Notation<br />Five- and Six-Variable K-Maps<br />Don’t cares<br />Gate propagation delay<br />The Mux<br />The Decoder<br />Implementing Circuits Using Muxes | ||
| − | | | + | |[[media:Mano_ch02_images.pdf|Chapter 2]]<br />[[media:Mano_ch03_images.pdf|Chapter 3]] |
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Revision as of 15:03, 9 May 2017
| LECTURE | DATE | MATERIAL | PREPARATION |
| 1 | AUG 28 | Course Introduction Number Systems Base Conversion Arithmetic Operations Codes |
Course Introduction Chapter 1 The Reflected Binary (Gray) Code |
| 2 | AUG 30 | Boolean Algebra The Consensus Theorem Introduction to K-Maps |
Chapter 2 |
| 3 | SEPT 6 | Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder |
Chapter 2 Chapter 3 |
| 4 | SEPT 11 | Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The Mux The Decoder Implementing Circuits Using Muxes |
Chapter 2 Chapter 3 |
| 5 | SEPT 13 | Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass) |
Standard Cell Circuit VHDL Tutorial Vivado Simulation Tutorial 1 Full Vivado Tutorial Boole's Expansion Theorem |
| 6 | SEPT 18 | Boole's Expansion Theorem (Second Pass) FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX) |
Chapter 5 |
| 7 | SEPT 20 | Digilent Development Board Concepts of VCCIO and Core Voltage Demo Board Schematic (LEDs, Switches) |
Manual Schematics |
