Difference between revisions of "Syllabus"
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|Digilent Development Board<br />Concepts of VCCIO and Core Voltage<br />Demo Board Schematic | |Digilent Development Board<br />Concepts of VCCIO and Core Voltage<br />Demo Board Schematic | ||
| − | | | + | |[[media:Dev_Board_Manual.pdf|Manual]]<br />[[media:Dev_Board_Schematics.pdf|Schematics]] |
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Revision as of 14:34, 9 May 2017
| LECTURE | DATE | MATERIAL | PREPARATION |
| 1 | AUG 28 | Course Introduction Number Systems Base Conversion Arithmetic Operations Codes |
Chapter 1 |
| 2 | AUG 30 | Boolean Algebra The Consensus Theorem Introduction to K-Maps |
Chapter 2 |
| 3 | SEPT 6 | Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder |
Chapter 2 |
| 4 | SEPT 11 | Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The Mux The Decoder Implementing Circuits Using Muxes |
Chapter 2 Chapter 3 |
| 5 | SEPT 13 | Standard Cell Implementation of Logic Circuits VHDL Tutorial VHDL Constructs: IF, WHEN, SELECT Vivado Simulation Tutorial Boole's Expansion Theorem (First Pass) |
Handouts |
| 6 | SEPT 18 | Boole's Expansion Theorem (Second Pass) FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX) |
Chapter 5 |
| 7 | SEPT 20 | Digilent Development Board Concepts of VCCIO and Core Voltage Demo Board Schematic |
Manual Schematics |
