Difference between revisions of "Syllabus"

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##Registers
 
##Registers
 
##State Diagrams
 
##State Diagrams
 +
##Finite State Machines (FSMs)
 +
##Mealy and Moore Models
 
##Finite-State Machine Synthesis
 
##Finite-State Machine Synthesis
 
##VHDL Representations
 
##VHDL Representations

Revision as of 19:54, 12 December 2016

  1. Digital Systems and Information
    1. Number Systems
    2. Base Conversion
    3. Arithmetic Operations
    4. Codes
  2. Combinational Logic Circuits
    1. Logic Gates
    2. Boolean Algebra
    3. K-Maps
    4. Sum of Products
    5. Product of Sums
    6. VHDL Representations
    7. FPGA LUT-based Implementation
  3. Combinational Logic Design
    1. Hierarchical Design Concepts
    2. Decoders/Encoders
    3. Multiplexers
    4. Binary Adders
    5. Subtraction/2s Complement
    6. Multiplication
    7. Division
  4. Sequential Circuits
    1. Latches
    2. Flip-Flops
    3. Registers
    4. State Diagrams
    5. Finite State Machines (FSMs)
    6. Mealy and Moore Models
    7. Finite-State Machine Synthesis
    8. VHDL Representations
    9. FPGA Implementations of FSMs
  5. Register Transfer Notation
    1. RTN Notation
    2. VHDL RTN Representations for Hardware Implementation of Register Transfers
      1. The Pipelined Difference Engine
      2. The Bus-Based Difference Engine
  6. Introduction to Microprocessors
    1. Extending the Bus-Based Difference Engine to the Really Simple RISC Computer
    2. The Really Simple RISC Computer
      1. Datapath
      2. Control FSM
      3. Displacement-Based Addressing
    3. RSRC Assembly Language and Simulator