Difference between revisions of "Lecture Notes"
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| + | [http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar SRC SIMULATOR] | ||
[http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial] | [http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial] | ||
[http://www.epanorama.net/documents/pc/vga_timing.html VGA Timing] | [http://www.epanorama.net/documents/pc/vga_timing.html VGA Timing] | ||
Revision as of 18:24, 16 November 2016
- Course Introduction
- Chapter 1
- -----The Reflected Binary (Gray) Code
- Chapter 2
- Chapter 3
- -----Synthesizable VHDL (2016 Version)
- -----Vivado Simulation Tutorial 1
- -----Vivado Simulation Tutorial 2 (Forcing a Clock)
- -----Full Vivado Tutorial (John MacKay)
- -----Boole's Expansion Theorem
- Chapter 4
- -----First Counter
- -----Second Counter
- -----Oscillators and Clock Distribution
- -----Definitions and Theorems for Sequential Machines
- -----Minimizing Completely Specified Machines
- Chapter 5
- Chapter 6
- Chapter 7
- Chapter 8
- Chapter 9
- Chapter 10
- Chapter 11
- Chapter 12
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
Links:
