Difference between revisions of "Lecture Notes"
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*[[media:Mano_ch05_images.pdf|Chapter 5]] | *[[media:Mano_ch05_images.pdf|Chapter 5]] | ||
*[[media:Mano_ch06_images.pdf|Chapter 6]] | *[[media:Mano_ch06_images.pdf|Chapter 6]] | ||
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| + | *[[media:RSRC_Block_Diagram.pdf|The Really Simple RISC Computer (RSRC)]] | ||
*[[media:SRC_Material.pdf|SRC Documentation]] | *[[media:SRC_Material.pdf|SRC Documentation]] | ||
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*[[media:Mano_ch07_images.pdf|Chapter 7]] | *[[media:Mano_ch07_images.pdf|Chapter 7]] | ||
*[[media:Mano_ch08_images.pdf|Chapter 8]] | *[[media:Mano_ch08_images.pdf|Chapter 8]] | ||
Revision as of 17:36, 16 November 2016
- Course Introduction
- Chapter 1
- -----The Reflected Binary (Gray) Code
- Chapter 2
- Chapter 3
- -----Synthesizable VHDL (2016 Version)
- -----Vivado Simulation Tutorial 1
- -----Vivado Simulation Tutorial 2 (Forcing a Clock)
- -----Full Vivado Tutorial (John MacKay)
- -----Boole's Expansion Theorem
- Chapter 4
- -----First Counter
- -----Second Counter
- -----Oscillators and Clock Distribution
- -----Definitions and Theorems for Sequential Machines
- -----Minimizing Completely Specified Machines
- Chapter 5
- Chapter 6
- Chapter 7
- Chapter 8
- Chapter 9
- Chapter 10
- Chapter 11
- Chapter 12
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
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