Difference between revisions of "Syllabus"
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|Course Introduction<br />Number Systems<br />Base Conversion<br />Arithmetic Operations<br />Codes | |Course Introduction<br />Number Systems<br />Base Conversion<br />Arithmetic Operations<br />Codes | ||
|[[media:Einstein.pdf|Course Introduction]]<br />[[media:Mano_ch01_images.pdf|Chapter 1]]<br />[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] | |[[media:Einstein.pdf|Course Introduction]]<br />[[media:Mano_ch01_images.pdf|Chapter 1]]<br />[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] | ||
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|Standard Forms: POS Notation<br />Two-Level Circuit Optimization Using K-Maps<br />Proving Identities Using K-Maps<br />The XOR Gate<br />The Half Adder<br />The Full Adder<br />The Ripple-Carry Adder | |Standard Forms: POS Notation<br />Two-Level Circuit Optimization Using K-Maps<br />Proving Identities Using K-Maps<br />The XOR Gate<br />The Half Adder<br />The Full Adder<br />The Ripple-Carry Adder | ||
|[[media:Mano_ch02_images.pdf|Chapter 2]]<br />[[media:Mano_ch03_images.pdf|Chapter 3]] | |[[media:Mano_ch02_images.pdf|Chapter 2]]<br />[[media:Mano_ch03_images.pdf|Chapter 3]] | ||
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|Standard Cell Implementation of Logic Circuits<br />VHDL: VHSIC Hardware Description Language<br />VHDL Constructs: IF, WHEN, SELECT<br />Xilnix Vivado Tool Suite<br />Boole's Expansion Theorem (First Pass) | |Standard Cell Implementation of Logic Circuits<br />VHDL: VHSIC Hardware Description Language<br />VHDL Constructs: IF, WHEN, SELECT<br />Xilnix Vivado Tool Suite<br />Boole's Expansion Theorem (First Pass) | ||
|[[media:Standard_Cell.JPG|Standard Cell Circuit]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:Vivado_Simulation_Tutorial.pdf|Vivado Simulation Tutorial 1]]<br />[[media:Vivado_Tutorial.pdf|Full Vivado Tutorial]]<br />[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] | |[[media:Standard_Cell.JPG|Standard Cell Circuit]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:Vivado_Simulation_Tutorial.pdf|Vivado Simulation Tutorial 1]]<br />[[media:Vivado_Tutorial.pdf|Full Vivado Tutorial]]<br />[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] | ||
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Revision as of 15:16, 9 May 2017
| LECTURE | DATE | MATERIAL | PREPARATION | ASSIGNED | DUE |
| 1 | AUG 28 | Course Introduction Number Systems Base Conversion Arithmetic Operations Codes |
Course Introduction Chapter 1 The Reflected Binary (Gray) Code |
Homework 1 | |
| 2 | AUG 30 | Boolean Algebra The Consensus Theorem Introduction to K-Maps |
Chapter 2 | ||
| 3 | SEPT 6 | Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder |
Chapter 2 Chapter 3 |
Homework 2 | Homework 1 |
| 4 | SEPT 11 | Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The Mux The Decoder Implementing Circuits Using Muxes |
Chapter 2 Chapter 3 |
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| 5 | SEPT 13 | Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass) |
Standard Cell Circuit VHDL Tutorial Vivado Simulation Tutorial 1 Full Vivado Tutorial Boole's Expansion Theorem |
Homework 3 | Homework 2 |
| 6 | SEPT 18 | Boole's Expansion Theorem (Second Pass) FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX) |
Chapter 5 | ||
| 7 | SEPT 20 | Digilent Development Board Concepts of VCCIO and Core Voltage Demo Board Schematic (LEDs, Switches) |
Manual Schematics |
Lab 1 | Homework 3 |
