Difference between revisions of "Syllabus"

Revision as of 14:47, 9 May 2017

SYLLABUS
LECTURE	DATE	MATERIAL	PREPARATION
1	AUG 28	Course Introduction Number Systems Base Conversion Arithmetic Operations Codes	Chapter 1
2	AUG 30	Boolean Algebra The Consensus Theorem Introduction to K-Maps	Chapter 2
3	SEPT 6	Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder	Chapter 2
4	SEPT 11	Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The Mux The Decoder Implementing Circuits Using Muxes	Chapter 2 Chapter 3
5	SEPT 13	Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass)	Standard Cell Circuit VHDL Tutorial Vivado Simulation Tutorial 1 Boole's Expansion Theorem
6	SEPT 18	Boole's Expansion Theorem (Second Pass) FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX)	Chapter 5
7	SEPT 20	Digilent Development Board Concepts of VCCIO and Core Voltage Demo Board Schematic (LEDs, Switches)	Manual Schematics

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 |SEPT 13
 |Standard Cell Implementation of Logic Circuits<br />VHDL: VHSIC Hardware Description Language<br />VHDL Constructs: IF, WHEN, SELECT<br />Xilnix Vivado Tool Suite<br />Boole's Expansion Theorem (First Pass)
-|[[media:Standard_Cell.JPG|Standard Cell Circuit]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]
+|[[media:Standard_Cell.JPG|Standard Cell Circuit]]<br />[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|VHDL Tutorial]]<br />[[media:Vivado_Simulation_Tutorial.pdf|Vivado Simulation Tutorial 1]]<br />[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]]
 |-