Difference between revisions of "Syllabus"
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###Control FSM | ###Control FSM | ||
###Displacement-Based Addressing | ###Displacement-Based Addressing | ||
+ | ###Memory | ||
+ | ####SRAM | ||
+ | ####DRAM | ||
+ | ####Address Decoding | ||
##RSRC Assembly Language and Simulator | ##RSRC Assembly Language and Simulator | ||
##RSRC VHDL Description and Implementation | ##RSRC VHDL Description and Implementation |
Revision as of 13:29, 24 April 2017
- Digital Systems and Information
- Number Systems
- Base Conversion
- Arithmetic Operations
- Codes
- Combinational Logic Circuits
- Logic Gates
- Boolean Algebra
- K-Maps
- Sum of Products
- Product of Sums
- VHDL Representations
- FPGA LUT-based Implementation
- Combinational Logic Design
- Hierarchical Design Concepts
- Decoders/Encoders
- Multiplexers
- Binary Adders
- Subtraction/2s Complement
- Multiplication
- Division
- Sequential Circuits
- Latches
- Flip-Flops
- Registers
- State Diagrams
- Finite State Machines (FSMs)
- Mealy and Moore Models
- Finite-State Machine Synthesis
- VHDL Representations
- FPGA Implementations of FSMs
- Register Transfer Notation
- RTN Notation
- VHDL RTN Representations for Hardware Implementation of Register Transfers
- The Pipelined Difference Engine
- The Bus-Based Difference Engine
- Introduction to Microprocessors
- Extending the Bus-Based Difference Engine to the Really Simple RISC Computer
- The Really Simple RISC Computer
- Datapath
- Control FSM
- Displacement-Based Addressing
- Memory
- SRAM
- DRAM
- Address Decoding
- RSRC Assembly Language and Simulator
- RSRC VHDL Description and Implementation