Difference between revisions of "General Information"
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Exam #3: TBD | Exam #3: TBD | ||
| − | Grading: | + | Grading: Exam 1: 33 1/3%; Exam 2: 33 1/3%; Exam 3: 33 1/3% |
Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity. | Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity. | ||
Three laboratories will be assigned during the semester. Laboratories must be done on an individual basis, and students collaborating with or submitting VHDL or bit files done by someone else for grading will be considered to have violated the course policy on academic integrity. | Three laboratories will be assigned during the semester. Laboratories must be done on an individual basis, and students collaborating with or submitting VHDL or bit files done by someone else for grading will be considered to have violated the course policy on academic integrity. | ||
Revision as of 20:54, 17 January 2017
Instructor, William D. Richard, Ph.D., Jolley Hall 538, 314-935-4676, wdr@wustl.edu
Office Hours: Tuesday/Thursday 9:00 - 11:00 a.m. or by appointment
Course Web Page: http://classes.engineering.wustl.edu/permanant/cse260m/index.php/Main_Page
Piazza Page: TBD
Student Resources Web Page: http://wps.pearsoned.com/ecs_mano_lcdf_5/248/63706/16308896.cw/index.html
Text: Logic and Computer Design Fundamentals (5th Edition), Mano/Kim/Martin, Prentice Hall, 2016, ISBN 0-13-376063-4.
Class Meeting: Mondays and Wednesdays, 1:00 - 2:30 p.m., Location: McMillan Hall G052
Exam #1: TBD
Exam #2: TBD
Exam #3: TBD
Grading: Exam 1: 33 1/3%; Exam 2: 33 1/3%; Exam 3: 33 1/3%
Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity.
Three laboratories will be assigned during the semester. Laboratories must be done on an individual basis, and students collaborating with or submitting VHDL or bit files done by someone else for grading will be considered to have violated the course policy on academic integrity.
