Difference between revisions of "Lecture Notes"

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*[[media:fermilab-conf-07-601-e.pdf|Fermilab ADC/TDC in FPGA Paper]]
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*[[media:Einstein.pdf|Course Introduction]]
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*[[media:CreatingAnADCUsingFPGAResources.pdf|Lattice Semiconductor ADC White Paper]]
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*[[media:Mano_ch01_images.pdf|Chapter 1]]
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*[[media:0714IFD1.pdf|Use Advanced PCB Technology to Produce 50% Smaller Product Designs]]
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*[[media:The_Reflected_Binary_(Gray)_Code.pdf|-----The Reflected Binary (Gray) Code]]
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*[[media:EVERYTHING_YOU_ALWAYS_WANTED.pdf|VHDL Lecture]]
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*[[media:Mano_ch02_images.pdf|Chapter 2]]
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*[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Machine Example]]
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*[[media:Mano_ch03_images.pdf|Chapter 3]]
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*[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]]
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*[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|-----Synthesizable VHDL (2016 Version)]]
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*[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]]
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*[[media:Vivado_Simulation_Tutorial.pdf|-----Vivado Simulation Tutorial 1]]
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*[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]]
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*[[media:Vivado_Simulation_Tutorial_2.pdf|-----Vivado Simulation Tutorial 2 (Forcing a Clock)]]
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*[[media:Employment Contract - Clean.pdf|Employment Contract]]
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*[[media:Vivado_Tutorial.pdf|-----Full Vivado Tutorial (John MacKay)]]
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*[[media:Boole’s_Expansion_Theorem.pdf|-----Boole's Expansion Theorem]]
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*[[media:Mano_ch04_images.pdf|Chapter 4]]
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*[[media:Norlatch.pdf|-----NOR SR Latch]]
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*[[media:First_Counter.pdf|-----First Counter]]
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*[[media:Second_Counter.pdf|-----Second Counter]]
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*[[media:Oscillators_and_Clock_Distribution.pdf|-----Oscillators and Clock Distribution]]
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*[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|-----Definitions and Theorems for Sequential Machines]]
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*[[media:Minimizing_Completely_Specified_Machines.pdf|-----Minimizing Completely Specified Machines]]
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*[[media:Metastability 1.pdf|-----Anomalous Behavior of Synchronizer and Arbiter Circuits]]
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*[[media:Metastability 2.pdf|-----Measured Flip-Flop Responses to Marginal Triggering]]
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 +
 
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*[[media:Mano_ch05_images.pdf|Chapter 5]]
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*[[media:Mano_ch06_images.pdf|Chapter 6]]
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*[[media:PID4703951.pdf|Using Babbage's Difference Engine to Introduce Computer Architecture (instructor Only)]]
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*[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]]
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*[[media:RSRC_CONTROL_VHDL.pdf|---RSRC CONTROL.VHD (Instructor Only)]]
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*[[media:ALU.pdf|---RSRC ALU.VHD (Instructor Only)]]
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*[[media:EPROM.pdf|---RSRC EPROM.VHD (Instructor Only)]]
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*[[media:SRAM.pdf|---RSRC SRAM.VHD (Instructor Only)]]
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*[[media:RSRC.pdf|---RSRC.VHD (Instructor Only)]]
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*[[media:TESTBENCH.pdf|---RSRC TESTBENCH.VHD (Instructor Only)]]
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*[[media:RSRC_Abstract_RTN.pdf|RSRC Abstract RTN]]
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*[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]]
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*[[media:DISPLACEMENT.pdf|RSRC/SRC Displacement-Based Addressing]]
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*[[media:SRC_Material.pdf|SRC Documentation]]
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*[[media:1_BUS_RSRC_BLOCK_DIAGRAM.pdf|---1-Bus SRC Block Diagram (From Heuring and Jordan)]]
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*[[media:2_BUS_RSRC_BLOCK_DIAGRAM.pdf|---2-Bus SRC Block Diagram (From Heuring and Jordan)]]
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*[[media:3_BUS_RSRC_BLOCK_DIAGRAM.pdf|---3-Bus SRC Block Diagram (From Heuring and Jordan)]]
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*[[media:3_BUS_RSRC_REGFILE.pdf|------3-Bus SRC Register File (From Heuring and Jordan)]]
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*[[media:Intel_8086_Block_Diagram.pdf|Intel 8086 Block Diagram]]
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*[[media:Difference_Engine_in_C.pdf|Difference Engine in C (x86)]]
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*[[media:Mano_ch07_images.pdf|Chapter 7]]
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*[[media:Mano_ch08_images.pdf|Chapter 8]]
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*[[media:Mano_ch09_images.pdf|Chapter 9]]
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*[[media:Mano_ch10_images.pdf|Chapter 10]]
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*[[media:Mano_ch11_images.pdf|Chapter 11]]
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*[[media:Mano_ch12_images.pdf|Chapter 12]]
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Links:
 
Links:
  
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[http://www.maximintegrated.com/en/app-notes/index.mvp/id/810 Understanding Flash ADCs]
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[http://classes.engineering.wustl.edu/cse362/images/8/89/Ch7CSDA.pdf CSE 362M Chapter 7]
  
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[https://davidkessner.wordpress.com/2011/05/01/adc-in-an-fpga/ ADC in an FPGA (Part 1)]
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[http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar SRC SIMULATOR]
  
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[https://davidkessner.wordpress.com/2011/06/05/adc-in-an-fpga-part-2/ ADC in an FPGA (Part 2)]
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[http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial]
  
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[http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics]
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[http://www.epanorama.net/documents/pc/vga_timing.html VGA Timing]

Latest revision as of 20:16, 9 May 2017





Links:

CSE 362M Chapter 7

SRC SIMULATOR

Vivado Clock Constraints Tutorial

VGA Timing

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