Difference between revisions of "Lecture Notes"
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*[[media:Einstein.pdf|Course Introduction]] | *[[media:Einstein.pdf|Course Introduction]] | ||
*[[media:Mano_ch01_images.pdf|Chapter 1]] | *[[media:Mano_ch01_images.pdf|Chapter 1]] | ||
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*[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|-----Definitions and Theorems for Sequential Machines]] | *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|-----Definitions and Theorems for Sequential Machines]] | ||
*[[media:Minimizing_Completely_Specified_Machines.pdf|-----Minimizing Completely Specified Machines]] | *[[media:Minimizing_Completely_Specified_Machines.pdf|-----Minimizing Completely Specified Machines]] | ||
| + | *[[media:Metastability 1.pdf|-----Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
| + | *[[media:Metastability 2.pdf|-----Measured Flip-Flop Responses to Marginal Triggering]] | ||
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*[[media:Mano_ch05_images.pdf|Chapter 5]] | *[[media:Mano_ch05_images.pdf|Chapter 5]] | ||
*[[media:Mano_ch06_images.pdf|Chapter 6]] | *[[media:Mano_ch06_images.pdf|Chapter 6]] | ||
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*[[media:3_BUS_RSRC_BLOCK_DIAGRAM.pdf|---3-Bus SRC Block Diagram (From Heuring and Jordan)]] | *[[media:3_BUS_RSRC_BLOCK_DIAGRAM.pdf|---3-Bus SRC Block Diagram (From Heuring and Jordan)]] | ||
*[[media:3_BUS_RSRC_REGFILE.pdf|------3-Bus SRC Register File (From Heuring and Jordan)]] | *[[media:3_BUS_RSRC_REGFILE.pdf|------3-Bus SRC Register File (From Heuring and Jordan)]] | ||
| − | + | *[[media:Intel_8086_Block_Diagram.pdf|Intel 8086 Block Diagram]] | |
| + | *[[media:Difference_Engine_in_C.pdf|Difference Engine in C (x86)]] | ||
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*[[media:Mano_ch11_images.pdf|Chapter 11]] | *[[media:Mano_ch11_images.pdf|Chapter 11]] | ||
*[[media:Mano_ch12_images.pdf|Chapter 12]] | *[[media:Mano_ch12_images.pdf|Chapter 12]] | ||
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Links: | Links: | ||
Latest revision as of 20:16, 9 May 2017
- Course Introduction
- Chapter 1
- -----The Reflected Binary (Gray) Code
- Chapter 2
- Chapter 3
- -----Synthesizable VHDL (2016 Version)
- -----Vivado Simulation Tutorial 1
- -----Vivado Simulation Tutorial 2 (Forcing a Clock)
- -----Full Vivado Tutorial (John MacKay)
- -----Boole's Expansion Theorem
- Chapter 4
- -----NOR SR Latch
- -----First Counter
- -----Second Counter
- -----Oscillators and Clock Distribution
- -----Definitions and Theorems for Sequential Machines
- -----Minimizing Completely Specified Machines
- -----Anomalous Behavior of Synchronizer and Arbiter Circuits
- -----Measured Flip-Flop Responses to Marginal Triggering
- Using Babbage's Difference Engine to Introduce Computer Architecture (instructor Only)
- The Really Simple RISC Computer (RSRC)
- ---RSRC CONTROL.VHD (Instructor Only)
- ---RSRC ALU.VHD (Instructor Only)
- ---RSRC EPROM.VHD (Instructor Only)
- ---RSRC SRAM.VHD (Instructor Only)
- ---RSRC.VHD (Instructor Only)
- ---RSRC TESTBENCH.VHD (Instructor Only)
- RSRC Abstract RTN
- 1Kx32 RSRC Memory Subsystem
- RSRC/SRC Displacement-Based Addressing
- SRC Documentation
- ---1-Bus SRC Block Diagram (From Heuring and Jordan)
- ---2-Bus SRC Block Diagram (From Heuring and Jordan)
- ---3-Bus SRC Block Diagram (From Heuring and Jordan)
- ------3-Bus SRC Register File (From Heuring and Jordan)
- Intel 8086 Block Diagram
- Difference Engine in C (x86)
Links:
