Difference between revisions of "Lecture Notes"
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| − | *[[media: | + | *[[media:Einstein.pdf|Course Introduction]] |
| − | *[[media: | + | *[[media:Mano_ch01_images.pdf|Chapter 1]] |
| − | *[[media: | + | *[[media:The_Reflected_Binary_(Gray)_Code.pdf|-----The Reflected Binary (Gray) Code]] |
| − | *[[media: | + | *[[media:Mano_ch02_images.pdf|Chapter 2]] |
| − | *[[media: | + | *[[media:Mano_ch03_images.pdf|Chapter 3]] |
| − | *[[media: | + | *[[media:EVERYTHING_YOU_ALWAYS_WANTED_2016.pdf|-----Synthesizable VHDL (2016 Version)]] |
| − | *[[media: | + | *[[media:Vivado_Simulation_Tutorial.pdf|-----Vivado Simulation Tutorial 1]] |
| − | *[[media: | + | *[[media:Vivado_Simulation_Tutorial_2.pdf|-----Vivado Simulation Tutorial 2 (Forcing a Clock)]] |
| − | *[[media: | + | *[[media:Vivado_Tutorial.pdf|-----Full Vivado Tutorial (John MacKay)]] |
| − | *[[media: | + | *[[media:Boole’s_Expansion_Theorem.pdf|-----Boole's Expansion Theorem]] |
| + | *[[media:Mano_ch04_images.pdf|Chapter 4]] | ||
| + | *[[media:Norlatch.pdf|-----NOR SR Latch]] | ||
| + | *[[media:First_Counter.pdf|-----First Counter]] | ||
| + | *[[media:Second_Counter.pdf|-----Second Counter]] | ||
| + | *[[media:Oscillators_and_Clock_Distribution.pdf|-----Oscillators and Clock Distribution]] | ||
| + | *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|-----Definitions and Theorems for Sequential Machines]] | ||
| + | *[[media:Minimizing_Completely_Specified_Machines.pdf|-----Minimizing Completely Specified Machines]] | ||
| + | *[[media:Metastability 1.pdf|-----Anomalous Behavior of Synchronizer and Arbiter Circuits]] | ||
| + | *[[media:Metastability 2.pdf|-----Measured Flip-Flop Responses to Marginal Triggering]] | ||
| + | |||
| + | |||
| + | *[[media:Mano_ch05_images.pdf|Chapter 5]] | ||
| + | *[[media:Mano_ch06_images.pdf|Chapter 6]] | ||
| + | |||
| + | |||
| + | *[[media:PID4703951.pdf|Using Babbage's Difference Engine to Introduce Computer Architecture (instructor Only)]] | ||
| + | *[[media:The_Really_Simple_RISC_Computer.pdf|The Really Simple RISC Computer (RSRC)]] | ||
| + | *[[media:RSRC_CONTROL_VHDL.pdf|---RSRC CONTROL.VHD (Instructor Only)]] | ||
| + | *[[media:ALU.pdf|---RSRC ALU.VHD (Instructor Only)]] | ||
| + | *[[media:EPROM.pdf|---RSRC EPROM.VHD (Instructor Only)]] | ||
| + | *[[media:SRAM.pdf|---RSRC SRAM.VHD (Instructor Only)]] | ||
| + | *[[media:RSRC.pdf|---RSRC.VHD (Instructor Only)]] | ||
| + | *[[media:TESTBENCH.pdf|---RSRC TESTBENCH.VHD (Instructor Only)]] | ||
| + | *[[media:RSRC_Abstract_RTN.pdf|RSRC Abstract RTN]] | ||
| + | *[[media:RSRC_4KB_Sync_SRAM.pdf|1Kx32 RSRC Memory Subsystem]] | ||
| + | *[[media:DISPLACEMENT.pdf|RSRC/SRC Displacement-Based Addressing]] | ||
| + | *[[media:SRC_Material.pdf|SRC Documentation]] | ||
| + | *[[media:1_BUS_RSRC_BLOCK_DIAGRAM.pdf|---1-Bus SRC Block Diagram (From Heuring and Jordan)]] | ||
| + | *[[media:2_BUS_RSRC_BLOCK_DIAGRAM.pdf|---2-Bus SRC Block Diagram (From Heuring and Jordan)]] | ||
| + | *[[media:3_BUS_RSRC_BLOCK_DIAGRAM.pdf|---3-Bus SRC Block Diagram (From Heuring and Jordan)]] | ||
| + | *[[media:3_BUS_RSRC_REGFILE.pdf|------3-Bus SRC Register File (From Heuring and Jordan)]] | ||
| + | *[[media:Intel_8086_Block_Diagram.pdf|Intel 8086 Block Diagram]] | ||
| + | *[[media:Difference_Engine_in_C.pdf|Difference Engine in C (x86)]] | ||
| + | |||
| + | |||
| + | *[[media:Mano_ch07_images.pdf|Chapter 7]] | ||
| + | *[[media:Mano_ch08_images.pdf|Chapter 8]] | ||
| + | *[[media:Mano_ch09_images.pdf|Chapter 9]] | ||
| + | *[[media:Mano_ch10_images.pdf|Chapter 10]] | ||
| + | *[[media:Mano_ch11_images.pdf|Chapter 11]] | ||
| + | *[[media:Mano_ch12_images.pdf|Chapter 12]] | ||
| + | |||
| + | |||
Links: | Links: | ||
| − | [http://www. | + | |
| + | [http://classes.engineering.wustl.edu/cse362/images/8/89/Ch7CSDA.pdf CSE 362M Chapter 7] | ||
| + | |||
| + | [http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar SRC SIMULATOR] | ||
| + | |||
| + | [http://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html Vivado Clock Constraints Tutorial] | ||
| + | |||
| + | [http://www.epanorama.net/documents/pc/vga_timing.html VGA Timing] | ||
Latest revision as of 20:16, 9 May 2017
- Course Introduction
- Chapter 1
- -----The Reflected Binary (Gray) Code
- Chapter 2
- Chapter 3
- -----Synthesizable VHDL (2016 Version)
- -----Vivado Simulation Tutorial 1
- -----Vivado Simulation Tutorial 2 (Forcing a Clock)
- -----Full Vivado Tutorial (John MacKay)
- -----Boole's Expansion Theorem
- Chapter 4
- -----NOR SR Latch
- -----First Counter
- -----Second Counter
- -----Oscillators and Clock Distribution
- -----Definitions and Theorems for Sequential Machines
- -----Minimizing Completely Specified Machines
- -----Anomalous Behavior of Synchronizer and Arbiter Circuits
- -----Measured Flip-Flop Responses to Marginal Triggering
- Using Babbage's Difference Engine to Introduce Computer Architecture (instructor Only)
- The Really Simple RISC Computer (RSRC)
- ---RSRC CONTROL.VHD (Instructor Only)
- ---RSRC ALU.VHD (Instructor Only)
- ---RSRC EPROM.VHD (Instructor Only)
- ---RSRC SRAM.VHD (Instructor Only)
- ---RSRC.VHD (Instructor Only)
- ---RSRC TESTBENCH.VHD (Instructor Only)
- RSRC Abstract RTN
- 1Kx32 RSRC Memory Subsystem
- RSRC/SRC Displacement-Based Addressing
- SRC Documentation
- ---1-Bus SRC Block Diagram (From Heuring and Jordan)
- ---2-Bus SRC Block Diagram (From Heuring and Jordan)
- ---3-Bus SRC Block Diagram (From Heuring and Jordan)
- ------3-Bus SRC Register File (From Heuring and Jordan)
- Intel 8086 Block Diagram
- Difference Engine in C (x86)
Links:
