Syllabus

FALL 2017

LECTURE	DATE	TOPICS	PREPARATION	ASSIGNED	DUE
1	AUG 28	Course Introduction Number Systems Base Conversion Arithmetic Operations Codes	Course Introduction Chapter 1 The Reflected Binary (Gray) Code	Homework 1
2	AUG 30	Boolean Algebra DeMorgan's Theorem The Consensus Theorem Introduction to K-Maps	Chapter 2
3	SEPT 6	Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder	Chapter 2 Chapter 3	Homework 2	Homework 1
4	SEPT 11	Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The 74LS04 Inverter The Mux The Decoder Implementing Circuits Using Muxes	Chapter 2 Chapter 3 74LS04 Datasheet
5	SEPT 13	Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass)	Standard Cell Circuit VHDL Tutorial Vivado Simulation Tutorial 1 Full Vivado Tutorial Boole's Expansion Theorem	Homework 3	Homework 2
6	SEPT 18	Boole's Expansion Theorem (Second Pass) Introduction to Xilinx 7-Series FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX)	Chapter 5 Xilinx 7-Series FPGAs Overview Xilinx 7-Series CLB User Guide
7	SEPT 20	Digilent Nexys4 DDR Development Board Digilent Nexys4 DDR Board Schematic (LEDs, Switches) Concepts of VCCIO and Core Voltage	Digilent Nexys4 DDR Manual Digilent Nexys4 DDR Schematics	Lab 1	Homework 3
8	SEPT 25	Implementing Functions with NAND and NOR Gates Implementing Functions with Decoders The Priority Encoder The 4-bit Adder as a 2-Level Circuit Addition and Subtraction of 2s Complement Numbers Incrementing (The Incrementer Circuit) Multiplication by Constants	Chapter 3
9	SEPT 27	Gate Propogation Delay Races and Hazards Review	Chapter 2		Lab 1
10	OCT 2	EXAM 1
11	OCT 4	Oscillators and Clock Distribution Flip-Flop as a Black Box A First Counter (Incrementer + FFs) The Difference Engine (DE) VHDL for FFs, Registers, Counters, and The DE Setup Time Hold Time Clock-to-Output Time Introduction to Metastability	Chapter 4 Oscillators and Clock Distribution First Counter Using Babbage's Difference Engine to Introduce Computer Architecture VHDL Tutorial Anomalous Behavior of Synchronizer and Arbiter Circuits Measured Flip-Flop Responses to Marginal Triggering	Homework 4
12	OCT 9	Latches NOR SR Latch VHDL Flip-Flops 74LS74/74S74 Flip-Flop Formal Definition of Mealy- and Moore-Model FSMs State Tables Second Counter: FSM Design Example Clocks in VHDL	Chapter 4 NOR SR Latch VHDL 74LS74 Datasheet Second Counter Vivado Simulation Tutorial 2 (Forcing a Clock)
13	OCT 11	Sequence Recognizer FSMs in VHDL One-Hot FSM Implementation Recognizing Character Sequences (Packet Sniffing)	Chapter 4 VHDL Tutorial	Homework 5 Lab 2	Homework 4
	OCT 16	Fall Break
14	OCT 18	FSM Timging/Max Clock Rate Path Analysis and Slack Equivalent States Minimizing Complete Specified Machines Combination Mealy/Moore Machines	Chapter 4 Vivado Clock Constraints Tutorial Definitions and Theorems for Sequential Machines Minimizing Completely Specified Machines
15	OCT 23	Digital Systems = Datapath + Control Register Transfers Tri-State Buffers Pull-ups/Pull-downs The Bus-Based Difference Engine	Chapter 6 The Really Simple RISC Computer (RSRC)	Homework 6 Lab 3	Homework 5 Lab 2
16	OCT 25	The Bus-Based Difference Engine Datapath VHDL Shift Registers Parallel-to-Serial Conversion Serial-to-Parallel Conversion Ripple Counters	Chapter 6 The Really Simple RISC Computer (RSRC)
17	OCT 30	The Bus-Based Difference Engine Control FSM VHDL	The Really Simple RISC Computer (RSRC)	Homework 6
18	NOV 1	Review			Lab 3
19	NOV 6	Exam 2
20	NOV 8	The Really Simple RISC Computer Simple Synchronous Static RAM Introduction to Assembly Language and Hand Assembly	The Really Simple RISC Computer (RSRC) 1Kx32 RSRC Memory Subsystem RSRC/SRC SIMULATOR	Homework 7
21	NOV 13	The Difference Engine in RSRC Assembly Language RSRC Instruction Fetch RTN ADD RTN Datapath Refinement RSRC Control FSM VHDL	The Really Simple RISC Computer (RSRC) RSRC Abstract RTN
22	NOV 15	Displacement-Based Addressing Branch Instruction Datapath Refinement Shift Instruction Datapath Refinement	The Really Simple RISC Computer (RSRC) RSRC/SRC Displacement-Based Addressing	Homework 8	Homework 7
23	NOV 20	R[rc] Multiplexor Design RSRC ALU VHDL 1Kx32 RSRC Memory Subsystem Memory: 6T SRAM Cell DRAM Cell	Chapter 7 The Really Simple RISC Computer (RSRC) 1Kx32 RSRC Memory Subsystem
24	NOV 27	A Commercial SRAM A Commercial DRAM A Commercial EPROM RSRC VHDL and Simulation Testbench	Cypress 32Kx8 SRAM Micron 4Mx16 EDO DRAM AMD 32Kx8 EPROM Datasheet The Really Simple RISC Computer (RSRC) RSRC VHDL Supplied by the Instructor	Homework 9	Homework 8
25	NOV 29	1-Bus vs. 2-Bus vs. 3-Bus RSRC 3-Bus RSRC Register File Intel 8086 Bus Architecture RSRC Instruction Set Review RSRC Architecture Review	1-Bus SRC Block Diagram (From Heuring and Jordan) 2-Bus SRC Block Diagram (From Heuring and Jordan) 3-Bus SRC Block Diagram (From Heuring and Jordan) 3-Bus SRC Register File (From Heuring and Jordan) Intel 8086 Block Diagram The Really Simple RISC Computer (RSRC)
26	DEC 4	Difference Engine in C (x86) w/Assembly Review	Difference Engine in C (x86)		Homework 9
27	DEC 6	Exam 3