Difference between revisions of "Syllabus"
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|OCT 4 | |OCT 4 | ||
− | | | + | |Oscillators and Clock Distribution<br />Flip-Flop as a Black Box<br />First Counter<br />The Difference Engine<br />VHDL for FFs, Registers, and The Difference Engine<br />Setup Time<br />Hold Time<br />Clock-to-Output Time<br />Introduction to Metastability |
− | | | + | |[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]]<br />[[media:Mano_ch04_images.pdf|Chapter 4]]<br />[[media:First_Counter.pdf|-----First Counter]]<br />[[media:Second_Counter.pdf|-----Second Counter]]<br />[[media:PID4703951.pdf|Using Babbage's Difference Engine to Introduce Computer Architecture]] |
− | | | + | |Homework 4 |
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Revision as of 16:05, 9 May 2017
LECTURE | DATE | MATERIAL | PREPARATION | ASSIGNED | DUE |
1 | AUG 28 | Course Introduction Number Systems Base Conversion Arithmetic Operations Codes |
Course Introduction Chapter 1 The Reflected Binary (Gray) Code |
Homework 1 | |
2 | AUG 30 | Boolean Algebra DeMorgan's Theorem The Consensus Theorem Introduction to K-Maps |
Chapter 2 | ||
3 | SEPT 6 | Standard Forms: POS Notation Two-Level Circuit Optimization Using K-Maps Proving Identities Using K-Maps The XOR Gate The Half Adder The Full Adder The Ripple-Carry Adder |
Chapter 2 Chapter 3 |
Homework 2 | Homework 1 |
4 | SEPT 11 | Essential Prime Implicants and Optimized Expressions Standard Forms: SOP Notation Five- and Six-Variable K-Maps Don’t cares Gate propagation delay The Mux The Decoder Implementing Circuits Using Muxes |
Chapter 2 Chapter 3 |
||
5 | SEPT 13 | Standard Cell Implementation of Logic Circuits VHDL: VHSIC Hardware Description Language VHDL Constructs: IF, WHEN, SELECT Xilnix Vivado Tool Suite Boole's Expansion Theorem (First Pass) |
Standard Cell Circuit VHDL Tutorial Vivado Simulation Tutorial 1 Full Vivado Tutorial Boole's Expansion Theorem |
Homework 3 | Homework 2 |
6 | SEPT 18 | Boole's Expansion Theorem (Second Pass) FPGAs USING LUTs to Implement Logic (LUT = Storage + MUX) |
Chapter 5 | ||
7 | SEPT 20 | Digilent Development Board Concepts of VCCIO and Core Voltage Demo Board Schematic (LEDs, Switches) |
Manual Schematics |
Lab 1 | Homework 3 |
8 | SEPT 25 | Implementing Functions with NAND and NOR Gates Implementing Functions with Decoders The Priority Encoder The 4-bit Adder as a 2-Level Circuit Addition and Subtraction of 2s Complement Numbers Incrementing (The Incrementer Circuit) Multiplication by Constants |
Chapter 3 | ||
9 | SEPT 27 | Gate Delay Races and Hazards |
Chapter 2 | Lab 1 | |
10 | OCT 2 | EXAM 1 | |||
11 | OCT 4 | Oscillators and Clock Distribution Flip-Flop as a Black Box First Counter The Difference Engine VHDL for FFs, Registers, and The Difference Engine Setup Time Hold Time Clock-to-Output Time Introduction to Metastability |
Oscillators and Clock Distribution Chapter 4 -----First Counter -----Second Counter Using Babbage's Difference Engine to Introduce Computer Architecture |
Homework 4 | |
12 | OCT 9 | ||||
13 | OCT 11 | ||||
OCT 16 | Fall Break | ||||
14 | OCT 18 | ||||
15 | OCT 23 | ||||
16 | OCT 25 | ||||
17 | OCT 30 | ||||
18 | NOV 1 | ||||
19 | NOV 6 | Exam 2 |