Difference between revisions of "Datasheets"

Latest revision as of 14:43, 4 May 2017

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-*[[media:Spartan6_Product_Brief.pdf|Xilinx Spartan 6 Product Brief]]
+*[[media:Sn74ls04.pdf|74LS04 Datasheet]]
-*[[media:ds160.pdf|Xilinx Spartan 6 LX Family Overview]]
+*[[media:Sn74ls74a.pdf|74LS74 Datasheet]]
-*[[media:ds162.pdf|Xilnx Spartan 6 LX Family Switching Characteristics]]
+*[[media:Am27c256.pdf|AMD 32Kx8 EPROM Datasheet]]
-*[[media:ug385.pdf|Xilinx Spartan 6 FPGA Packaging and Pinouts]]
+*[[media:Cy7c199n_8.pdf|Cypress 32Kx8 SRAM]]
-*[[media:spartan6_hdl.pdf|Xilinx Spartan 6 Libraries Guide for HDL (see page 225)]]
+*[[media:MT4LC4M16R6.pdf|Micron 4Mx16 EDO DRAM]]
-*[[media:wp396_S6_HV_Perf_Power.pdf|Xilinx High-Volume Spartan 6 FPGAs Whitepaper]]
-*[[media:wp420-DDR3-SI-PCB.pdf|Xilinx Virtex 6/Spartan 6 DDR3/PCB Whitepaper]]
-*[[media:QTH.pdf|SAMTEC Header]]
-*[[media:I2C Specification.pdf|I2C Specification]]
+*[[media:Ds180_7Series_Overview.pdf|Xilinx 7-Series FPGAs Overview]]
+*[[media:Ug474_7Series_CLB.pdf|Xilinx 7-Series CLB User Guide]]
+*[[media:Ug903-vivado-using-constraints.pdf|Vivado Design Suite User Guide: Using Constraints]]
+*[[media:Dev_Board_Manual.pdf|Digilent NEXYS 4 DDR Development Board Manual]]
+*[[media:Dev_Board_Schematics.pdf|Digilent NEXYS 4 DDR Development Board Schematics]]