|
|
| (59 intermediate revisions by the same user not shown) |
| Line 1: |
Line 1: |
| − | *[[media:USB3_r1.0_06_06_2011.pdf|USB 3.0 Specification (from USB.org)]] | + | *[[media:Sn74ls04.pdf|74LS04 Datasheet]] |
| − | *[[media:FX3_Datasheet.pdf|Cypress FX3 Datasheet]]
| + | *[[media:Sn74ls74a.pdf|74LS74 Datasheet]] |
| − | *[[media:FX3_Development_Kit_User_Guide.pdf|FX3 Development Kit User Guide]] | + | *[[media:Am27c256.pdf|AMD 32Kx8 EPROM Datasheet]] |
| − | *[[media:FX3_Development_Kit_Quick_Start_Guide.pdf|FX3 Development Kit Quick Start Guide]] | + | *[[media:Cy7c199n_8.pdf|Cypress 32Kx8 SRAM]] |
| − | *[[media:FX3-DVK-BOARD-DEVICE_REV3_08-29.pdf|FX3 Development Board Schematics]]
| + | *[[media:MT4LC4M16R6.pdf|Micron 4Mx16 EDO DRAM]] |
| − | *[[media:FX3_Slave_FIFO_Interface.pdf|Cypress FX3 Slave FIFO Interface Application Note]] | + | |
| − | *[[media:Sp601_product_brief.pdf|Xilinx SP601 Evaluation Kit Product Brief]] | + | |
| − | *[[media:Ug518.pdf|Xilinx SP601 User Guide]]
| + | *[[media:Ds180_7Series_Overview.pdf|Xilinx 7-Series FPGAs Overview]] |
| − | *[[media:Ug523.pdf|Xilinx SP601 Getting Started with the SP601]]
| + | *[[media:Ug474_7Series_CLB.pdf|Xilinx 7-Series CLB User Guide]] |
| − | *[[media:Xtp049.pdf|Xilinx SP601 Hardware Setup Guide]] | + | |
| − | *[[media:Xtp051_sp601_schematics.pdf| Xilinx SP601 Schematics]]
| + | |
| − | *[[media:QSH_To_FMC_and_QSH_To_HSMC_Bridge_Boards_Rev_2.0_Schematics_.pdf|Agile Solutions Adapter Schematics]]
| + | *[[media:Ug903-vivado-using-constraints.pdf|Vivado Design Suite User Guide: Using Constraints]] |
| − | *[[media:Ds160.pdf|Xilinx Spartan 6 LX Family Overview]]
| + | |
| − | *[[media:Ds162.pdf|Xilnx Spartan 6 LX Family Switching Characteristics]] | + | |
| − | *[[media:Ug385.pdf|Xilinx Spartan 6 FPGA Packaging and Pinouts]]
| + | *[[media:Dev_Board_Manual.pdf|Digilent NEXYS 4 DDR Development Board Manual]] |
| − | *[[media:Spartan6_hdl.pdf|Xilinx Spartan 6 Libraries Guide for HDL (see page 225)]]
| + | *[[media:Dev_Board_Schematics.pdf|Digilent NEXYS 4 DDR Development Board Schematics]] |
| − | *[[media:Ug382.pdf|Xilinx Spartan 6 FPGA Clock Resources User Guide (see page 113)]]
| |
| − | *[[media:Ds090.pdf|Xilinx CoolRunner-II CPLD Family Datasheet]]
| |
| − | *[[media:Ds311.pdf|Xilinx CoolRunner-II XC2C64 CPLD Datasheet]] | |
| − | *[[media:Ecs-3518-3525r.pdf|ECS 3518/3525 SMT Oscillator Datasheet]]
| |
| − | *[[media:878322620_sd.pdf|JTAG Header Footprint]]
| |
| − | *[[media:Tlv70018.pdf|TLV700xx 1.8V/2.5V LDO Regulator Datasheet]]
| |
| − | *[[media:PLX_Technology_USB_Duet_Technology.pdf|PLX Duet Technology]]
| |
| − | *[[media:Cast_usbss-dev-x.pdf|CAST USB 3.0 Xilinx Core]] | |
| − | *[[media:Datasheet_USB3.pdf|Innovative Logic USB 3.0 Core]] | |
| − | *[[media:Usbex280_brochure.pdf|Ellisys USB Explorer 280]]
| |
| − | *[[media:QTH.pdf|SAMTEC Header]]
| |
| − | *[[media:I2C Specification.pdf|I2C Specification]]
| |
