Difference between revisions of "Lecture Notes"
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[http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar SRC SIMULATOR] | [http://classes.engineering.wustl.edu/cse362/index.php/File:SRCToolsv3.1.1.jar SRC SIMULATOR] | ||
Revision as of 13:24, 18 April 2017
- Course Introduction
- Chapter 1
- -----The Reflected Binary (Gray) Code
- Chapter 2
- Chapter 3
- -----Synthesizable VHDL (2016 Version)
- -----Vivado Simulation Tutorial 1
- -----Vivado Simulation Tutorial 2 (Forcing a Clock)
- -----Full Vivado Tutorial (John MacKay)
- -----Boole's Expansion Theorem
- Chapter 4
- -----NOR SR Latch
- -----First Counter
- -----Second Counter
- -----Oscillators and Clock Distribution
- -----Definitions and Theorems for Sequential Machines
- -----Minimizing Completely Specified Machines
- Chapter 5
- Chapter 6
- Using Babbage's Difference Engine to Introduce Computer Architecture
- The Really Simple RISC Computer (RSRC)
- RSRC Abstract RTN
- 1Kx32 RSRC Memory Subsystem
- RSRC CONTROL.VHD (Instructor Only)
- RSRC ALU.VHD (Instructor Only)
- RSRC/SRC Displacement-Based Addressing
- SRC Documentation
- Chapter 7
- Chapter 8
- Chapter 9
- Chapter 10
- Chapter 11
- Chapter 12
- Anomalous Behavior of Synchronizer and Arbiter Circuits
- Measured Flip-Flop Responses to Marginal Triggering
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