Difference between revisions of "Syllabus"
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##State Diagrams | ##State Diagrams | ||
##Finite State Machines (FSMs) | ##Finite State Machines (FSMs) | ||
− | ##Mealy and Moore Models | + | ###Mealy and Moore Models |
− | ##Finite-State Machine Synthesis | + | ###Finite-State Machine Synthesis |
− | ##VHDL Representations | + | ###VHDL Representations |
− | ##FPGA Implementations of FSMs | + | ###FPGA Implementations of FSMs |
#Register Transfer Notation | #Register Transfer Notation | ||
##RTN Notation | ##RTN Notation |
Revision as of 19:54, 12 December 2016
- Digital Systems and Information
- Number Systems
- Base Conversion
- Arithmetic Operations
- Codes
- Combinational Logic Circuits
- Logic Gates
- Boolean Algebra
- K-Maps
- Sum of Products
- Product of Sums
- VHDL Representations
- FPGA LUT-based Implementation
- Combinational Logic Design
- Hierarchical Design Concepts
- Decoders/Encoders
- Multiplexers
- Binary Adders
- Subtraction/2s Complement
- Multiplication
- Division
- Sequential Circuits
- Latches
- Flip-Flops
- Registers
- State Diagrams
- Finite State Machines (FSMs)
- Mealy and Moore Models
- Finite-State Machine Synthesis
- VHDL Representations
- FPGA Implementations of FSMs
- Register Transfer Notation
- RTN Notation
- VHDL RTN Representations for Hardware Implementation of Register Transfers
- The Pipelined Difference Engine
- The Bus-Based Difference Engine
- Introduction to Microprocessors
- Extending the Bus-Based Difference Engine to the Really Simple RISC Computer
- The Really Simple RISC Computer
- Datapath
- Control FSM
- Displacement-Based Addressing
- RSRC Assembly Language and Simulator