Design Problem for HWK#6:

4. What is the low output level for a pseudo-nMOS two input NOR gate if nFETS and pFETS have W=4 lambda, and L= 2 lambda for all FETS? Vdd = 2.5V.

5. What is the delay for a minimum size inverter (W=4 lambda for both FETS) with 1pF load? For 10-input NAND and NOR gates with minimum size FETS and 1pF load? State clearly any assumptions.